5127c5d9b2
Preserve line number information while converting Invoke into a Call.
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llvm-svn: 132505
2011-06-02 22:46:58 +00:00
02da72f60e
This should have been a C++ testcase.
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llvm-svn: 132504
2011-06-02 22:26:15 +00:00
e242ebea50
Just use a SmallVector.
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I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.
This should fix the test failures on darwin 9.
llvm-svn: 132500
2011-06-02 22:22:43 +00:00
f86a53493e
Testcase for r132493.
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llvm-svn: 132495
2011-06-02 22:12:42 +00:00
8eced30568
Update for r132493 change.
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llvm-svn: 132494
2011-06-02 22:11:49 +00:00
5ca0837397
Remove dead code.
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llvm-svn: 132488
2011-06-02 21:31:00 +00:00
f02a376fbc
Update DBG_VALUEs while breaking anti dependencies.
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llvm-svn: 132487
2011-06-02 21:26:52 +00:00
f0759ef271
Fix encoding for VEXTdf.
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llvm-svn: 132486
2011-06-02 21:25:24 +00:00
5da0ff41d7
PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid.
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llvm-svn: 132485
2011-06-02 21:24:42 +00:00
e5feef0fe1
During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
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Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!
llvm-svn: 132483
2011-06-02 20:07:12 +00:00
e37b939793
Add test for PR10068.
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llvm-svn: 132482
2011-06-02 20:02:48 +00:00
aa318ae495
Revert 132424 to fix PR10068.
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llvm-svn: 132479
2011-06-02 19:57:47 +00:00
351422bdc8
Andy pointed out a dumb omission in this test case. Thanks Andy!
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llvm-svn: 132477
2011-06-02 19:26:49 +00:00
ca9b7bbaa1
Add a new parse hint for multi-letter constraints in inline asm.
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Testcase will come when we use it.
Part of rdar://9119939
llvm-svn: 132476
2011-06-02 19:26:37 +00:00
e239a6920e
Jakob pointed out a dumb omission in this test case. Thanks Jakob!
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llvm-svn: 132472
2011-06-02 18:44:05 +00:00
50663b7485
Use RegisterClassInfo::getOrder in RAFast.
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This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.
llvm-svn: 132471
2011-06-02 18:35:30 +00:00
dac0238ed2
.cfi directive register parsing flexibility.
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Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.
llvm-svn: 132466
2011-06-02 17:14:04 +00:00
8d530ad22a
Omit unnecessary stack copy when x87 input is a load.
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rdar://problem/6373334
llvm-svn: 132458
2011-06-02 15:57:11 +00:00
c8c4f7640a
Start with a zeroed CSRNum map.
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Found by valgrind.
llvm-svn: 132457
2011-06-02 12:07:44 +00:00
09e6667531
Initialize members to fix problem found by valgrind.
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llvm-svn: 132456
2011-06-02 05:43:49 +00:00
aff1060207
Use TRI::has{Sub,Super}ClassEq() where possible.
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No functional change.
llvm-svn: 132455
2011-06-02 05:43:46 +00:00
7f25c32d5b
Tweak testcase for ARM bot. rdar://problem/5993888
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llvm-svn: 132454
2011-06-02 05:05:39 +00:00
d6860522b2
Don't hardcode the %reg format in the streamer.
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llvm-svn: 132451
2011-06-02 02:34:55 +00:00
c58894bc36
Add a RegisterClassInfo class that lazily caches information about
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register classes.
It provides information for each register class that cannot be
determined statically, like:
- The number of allocatable registers in a class after filtering out the
reserved and invalid registers.
- The preferred allocation order with registers that overlap callee-saved
registers last.
- The last callee-saved register that overlaps a given physical register.
This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible. The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.
Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.
llvm-svn: 132450
2011-06-02 02:19:35 +00:00
2446869410
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
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llvm-svn: 132448
2011-06-02 01:03:14 +00:00
d84c76f2a7
Test case for r132444.
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llvm-svn: 132445
2011-06-02 00:25:53 +00:00
6627752050
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
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llvm-svn: 132444
2011-06-02 00:24:44 +00:00
b576b1675c
When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though.
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In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated).
The included testcase tests both this commit and r132434.
Part two of rdar://9429882. (r132434 was mislabeled.)
llvm-svn: 132442
2011-06-02 00:08:52 +00:00
6ded76be9c
Typos.
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llvm-svn: 132437
2011-06-01 23:32:40 +00:00
4b6eeb9ca2
In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 .
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Testcase coming up soon.
llvm-svn: 132434
2011-06-01 23:16:53 +00:00
e7181b5fdb
A DBG_VALUE that truncates a range does not start another dbg value range.
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llvm-svn: 132433
2011-06-01 23:00:17 +00:00
324f843107
Do not drop constant values when a variable's content is described using .debug_loc entries.
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llvm-svn: 132427
2011-06-01 22:03:25 +00:00
7adc95f69e
Recommit 132404 with fixes. rdar://problem/5993888
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llvm-svn: 132424
2011-06-01 21:33:14 +00:00
690030c116
Allow bitcasts between valid types of the same size and vector
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types if the vector type is legal.
Fixes rdar://9306086
llvm-svn: 132420
2011-06-01 19:55:10 +00:00
aab130d995
Revert 132404 to appease a buildbot. rdar://problem/5993888
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llvm-svn: 132419
2011-06-01 19:52:20 +00:00
22ad9bb7d9
Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use
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the TargetLowering enum.
llvm-svn: 132418
2011-06-01 19:47:10 +00:00
8ef3ad049d
SCEV: missing null check fix for r132360, dragonegg crash.
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llvm-svn: 132416
2011-06-01 19:14:56 +00:00
e9cc8e90b7
Revert r132358 "Simplify the eviction policy by making the failsafe explicit."
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This commit caused regressions in i386 flops-[568], matrix, salsa20,
256.bzip2, and enc-md5.
llvm-svn: 132413
2011-06-01 18:45:02 +00:00
3ae49c03a4
Fix double FGETSIGN to work on x86_32; followup to 132396.
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rdar://problem/5660695
llvm-svn: 132411
2011-06-01 18:32:25 +00:00
d949eb714a
Add a testcase, enabled only on arm, for llvm-gcc r132366.
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llvm-svn: 132409
2011-06-01 18:23:56 +00:00
41b1aa466d
Cleanup test case. rdar://problem/5660695
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llvm-svn: 132408
2011-06-01 18:23:14 +00:00
10539ada05
Initialize IssueWidth to zero.
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Fixes valgrind errors in the CellSPU backend.
llvm-svn: 132405
2011-06-01 17:19:08 +00:00
7b7c102f2c
Add support for x86 CMPEQSS and friends. These instructions do a
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floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
llvm-svn: 132404
2011-06-01 17:17:45 +00:00
2380483355
Reapply 132348 with fixes. rdar://problem/6501862
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llvm-svn: 132402
2011-06-01 16:42:47 +00:00
6f89e2ffaa
A forthcoming SSE patch will break this test; since the test is also
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valid for x87, re-target to x87. rdar://problem/5993888
llvm-svn: 132401
2011-06-01 16:13:09 +00:00
4d2fe66dc0
Test case for 132396. rdar://problem/5660695
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llvm-svn: 132399
2011-06-01 15:50:29 +00:00
56ce3a0f01
Fix PR10059 and future variations by handling all register subclasses.
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Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.
llvm-svn: 132398
2011-06-01 15:32:10 +00:00
fd5ecd0cec
Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695
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llvm-svn: 132396
2011-06-01 14:04:17 +00:00
af5f23ee07
Add new -d option to tblgen. It writes a make(1)-style dependency file.
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llvm-svn: 132395
2011-06-01 13:10:15 +00:00
8b24a731f2
This patch is another step in the direction of adding vector select. In this
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patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization. This flag will be removed when the transition is
complete.
llvm-svn: 132394
2011-06-01 12:51:46 +00:00
Devang Patel