d08fbd19f5
Move callee-saved regs spills / reloads to TFI
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llvm-svn: 120228
2010-11-27 23:05:03 +00:00
e3d864b857
convert targets to the new MF.getMachineMemOperand interface.
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llvm-svn: 114391
2010-09-21 04:39:43 +00:00
8289f78569
Remove the isMoveInstr() hook.
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llvm-svn: 108567
2010-07-16 22:35:46 +00:00
499f797cdd
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
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thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
65306369ae
Replace copyRegToReg with copyPhysReg for MSP430.
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llvm-svn: 108080
2010-07-11 06:53:30 +00:00
0125b6410a
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
2010-06-17 22:43:56 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
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llvm-svn: 104421
2010-05-22 01:47:14 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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llvm-svn: 103193
2010-05-06 19:06:44 +00:00
ebbdfef2fc
Implement indirect branches on MSP430
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llvm-svn: 102835
2010-05-01 12:04:32 +00:00
60b289709e
Educate GetInstrSizeInBytes implementations that
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DBG_VALUE does not generate code.
llvm-svn: 100681
2010-04-07 19:51:44 +00:00
6f306d7d30
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
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llvm-svn: 100214
2010-04-02 20:16:16 +00:00
4244d12769
Teach AnalyzeBranch, RemoveBranch and the branch
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folder to be tolerant of debug info following the
branch(es) at the end of a block.
llvm-svn: 100168
2010-04-02 01:38:09 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
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into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
ce52fd5f93
Add branch relaxation pass (shamelessly stolen from PPC).
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llvm-svn: 93554
2010-01-15 21:19:05 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
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MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
a48f44d9ee
improve portability to avoid conflicting with std::next in c++'0x.
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Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
e61e0b9a74
Add few pseudo-source-values
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llvm-svn: 86383
2009-11-07 17:13:57 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
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llvm-svn: 84775
2009-10-21 19:17:55 +00:00
5399c2d05e
Implement branch folding
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llvm-svn: 84774
2009-10-21 19:17:18 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
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This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
56d0659726
assert(0) -> LLVM_UNREACHABLE.
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
f7b83c7ae7
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
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booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
llvm-svn: 71722
2009-05-13 21:33:08 +00:00
41917df643
Add InsertBranch() hook for tail mergeing
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llvm-svn: 70754
2009-05-03 13:15:22 +00:00
1af0b61e7c
Add code for save/restore of callee-saved registers
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llvm-svn: 70739
2009-05-03 13:11:04 +00:00
f6af822c76
First draft of stack slot loads / stores lowering
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llvm-svn: 70735
2009-05-03 13:09:57 +00:00
ec3f0b3f9d
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
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llvm-svn: 70728
2009-05-03 13:07:54 +00:00
80a73e7d8b
Add 8-bit insts. zext behaviour is not modelled yet
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llvm-svn: 70722
2009-05-03 13:05:42 +00:00
d7afd69e3b
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
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llvm-svn: 70710
2009-05-03 13:02:04 +00:00
101380015c
Dummy MSP430 backend
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llvm-svn: 70694
2009-05-03 12:57:15 +00:00
Anton Korobeynikov