e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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llvm-svn: 78244
2009-08-05 21:02:22 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
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llvm-svn: 78086
2009-08-04 18:46:17 +00:00
1f58eed638
Add VFP3 D registers to the DPR register class.
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llvm-svn: 77521
2009-07-29 23:03:41 +00:00
eadb6681cf
Fix a obvious copy-n-paste bug.
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llvm-svn: 76727
2009-07-22 06:12:40 +00:00
d214b72962
Model fpscr to prevent fcmped / fcmpezs etc from being deleted.
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llvm-svn: 76390
2009-07-20 02:12:31 +00:00
7bbb9a91ab
Fix an obvious copy-and-paste error.
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llvm-svn: 75566
2009-07-14 00:23:44 +00:00
acb9927fd8
Revert 75309.
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llvm-svn: 75562
2009-07-14 00:01:42 +00:00
a51f8ebf1a
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
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quad registers and the Q4PR class holds sets of 4 quad registers.
llvm-svn: 75309
2009-07-10 23:09:06 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
a0ca298f8a
Remove UseThumbBacktraces. Just check if subtarget is darwin.
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llvm-svn: 73734
2009-06-18 23:14:30 +00:00
77d1943637
The attached patches implement most of the ARM AAPCS-VFP hard float
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ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
3158790e32
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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llvm-svn: 72955
2009-06-05 19:08:58 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
a7f77599a4
Added ARM::CPSR to represent ARM CPSR status register.
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llvm-svn: 37897
2007-07-05 07:17:13 +00:00
e656d093a5
Specify S registers as D registers' sub-registers.
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llvm-svn: 36280
2007-04-20 21:20:10 +00:00
e94a2f8026
Change register allocation order to Dale's suggestion.
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llvm-svn: 35021
2007-03-08 02:56:40 +00:00
17cdad0687
ARM always use register scavenger. No longer reserves R12.
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llvm-svn: 34999
2007-03-07 02:46:23 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
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llvm-svn: 34711
2007-02-28 00:59:19 +00:00
9049cd72e6
Temporary: make R12 available in ARM mode if RegScavenger is being used.
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llvm-svn: 34709
2007-02-28 00:22:44 +00:00
ee8aca0cfa
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function.
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llvm-svn: 34701
2007-02-27 23:03:55 +00:00
8953edc8a5
Comment.
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llvm-svn: 33633
2007-01-29 22:23:02 +00:00
16e58be1bc
hasFP() is now a virtual method of MRegisterInfo.
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llvm-svn: 33455
2007-01-23 00:57:47 +00:00
aa24f08926
Clean up ARM PEI code.
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llvm-svn: 33389
2007-01-20 02:09:25 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
a23166d6a4
initial support for frame pointers
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llvm-svn: 31197
2006-10-26 13:31:26 +00:00
d55c0a41df
fix the names of the 64bit fp register
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initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
53f78be49e
add floating point registers
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implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
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llvm-svn: 29756
2006-08-17 22:00:08 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
David Goodwin