85b5b027f7
Use NEON for single-precision int<->FP conversions.
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llvm-svn: 78604
2009-08-10 22:17:39 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
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llvm-svn: 78101
2009-08-04 20:39:05 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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llvm-svn: 78081
2009-08-04 17:53:06 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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llvm-svn: 77242
2009-07-27 19:59:26 +00:00
a0b2dc93b5
Fix typo in addrmode definition.
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llvm-svn: 76806
2009-07-22 22:24:31 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
81cdd21dcb
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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llvm-svn: 75254
2009-07-10 17:03:29 +00:00
5edd90cbbc
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
f731a2df6b
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
14965760a7
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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llvm-svn: 74988
2009-07-08 01:46:35 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
d76f0be844
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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llvm-svn: 74158
2009-06-25 02:08:06 +00:00
bec1dba896
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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llvm-svn: 73985
2009-06-23 19:38:13 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
fabdcce677
Handle the rest of pseudo instructions.
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llvm-svn: 59275
2008-11-13 23:36:57 +00:00
2666f59322
Fix pre- and post-indexed load / store encoding bugs.
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llvm-svn: 59230
2008-11-13 07:34:59 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
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llvm-svn: 59107
2008-11-12 07:18:38 +00:00
4b6c7efbde
Fix VFP conversion instruction encodings.
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llvm-svn: 59104
2008-11-12 06:41:41 +00:00
97ccab888a
Fix FMDRR encoding.
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llvm-svn: 59088
2008-11-11 22:46:12 +00:00
8cbbcb1f2f
Encode VFP load / store instructions.
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llvm-svn: 59084
2008-11-11 21:48:44 +00:00
38c9a14a88
Encode VFP conversion instructions.
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llvm-svn: 59074
2008-11-11 19:40:26 +00:00
ac2af2fdb2
Encode VFP arithmetic instructions.
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llvm-svn: 59016
2008-11-11 02:11:05 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
453844c352
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
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llvm-svn: 58707
2008-11-04 17:57:07 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
b7c01f5f48
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
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llvm-svn: 57524
2008-10-14 20:36:24 +00:00
7848cfcd77
Fix addrmode1 instruction encodings; fix bx_ret encoding.
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llvm-svn: 56277
2008-09-17 07:53:38 +00:00
937569afe3
Specify instruction encoding using range list to avoid endianess issues.
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llvm-svn: 56276
2008-09-17 07:16:21 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
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llvm-svn: 56176
2008-09-12 23:15:39 +00:00
d1424c4eca
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
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llvm-svn: 56172
2008-09-12 22:45:55 +00:00
David Goodwin