c3c949b473
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
58698d2534
More effective breakdown of memcpy into repeated load/store. These are now
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in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
llvm-svn: 37179
2007-05-17 21:31:21 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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llvm-svn: 36506
2007-04-27 13:54:47 +00:00
ee2d164f0f
Implement PIC for arm-linux.
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llvm-svn: 36324
2007-04-22 00:04:12 +00:00
d44e24c896
remove dead target hooks
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llvm-svn: 35846
2007-04-09 23:33:39 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
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llvm-svn: 35840
2007-04-09 22:27:04 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
1eb94d973a
implement the new addressing mode description hook.
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llvm-svn: 35521
2007-03-30 23:15:24 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
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llvm-svn: 35406
2007-03-28 01:53:55 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
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not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
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llvm-svn: 35245
2007-03-21 21:51:52 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
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instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
8447d34903
fix obvious comment bug
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llvm-svn: 35196
2007-03-20 00:30:56 +00:00
0e34d6af6b
Added isLegalAddressExpression(). Only allows X +/- C for now.
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llvm-svn: 35122
2007-03-16 08:43:56 +00:00
2150b9286f
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
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llvm-svn: 35075
2007-03-12 23:30:29 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Evan Cheng