Commit Graph

109 Commits

Author SHA1 Message Date
Benjamin Kramer bc6666bedf InlineSpiller: Store bucket pointers instead of iterators.
Lets us use a SetVector instead of an explicit set + vector combination.

llvm-svn: 182586
2013-05-23 15:42:57 +00:00
Benjamin Kramer 391f5a6e21 InlineSpiller: Remove quadratic behavior.
No functionality change.

llvm-svn: 181149
2013-05-05 11:29:14 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jakob Stoklund Olesen 26c9d70d28 Make the LiveRegMatrix analysis available to targets.
No functional change, just moved header files.

Targets can inject custom passes between register allocation and
rewriting. This makes it possible to tweak the register allocation
before rewriting, using the full global interference checking available
from LiveRegMatrix.

llvm-svn: 168806
2012-11-28 19:13:06 +00:00
James Molloy 381fab93d5 Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses an instruction's use of a physical register, analogous to analyzeVirtReg.
Rename RegInfo to VirtRegInfo so as not to be confused with the new PhysRegInfo.

llvm-svn: 163694
2012-09-12 10:03:31 +00:00
Logan Chien 64f361e0e1 Fix typo.
llvm-svn: 163059
2012-09-01 12:11:41 +00:00
Jakob Stoklund Olesen 8f324a2cc8 Account for early-clobber reload instructions.
No test case, there are no in-tree targets that require this.

llvm-svn: 160219
2012-07-14 18:45:35 +00:00
Jakob Stoklund Olesen 45c1f9976c Print out register number in InlineSpiller.
llvm-svn: 158575
2012-06-15 23:47:09 +00:00
Benjamin Kramer 009b1c1cf1 Round 2 of dead private variable removal.
LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

llvm-svn: 158096
2012-06-06 19:47:08 +00:00
Jakob Stoklund Olesen 2aeead4bf6 Use LiveRangeQuery instead of getLiveRangeContaining().
llvm-svn: 157142
2012-05-20 02:44:33 +00:00
Pete Cooper 3ca96f9950 Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen
llvm-svn: 153906
2012-04-02 22:44:18 +00:00
Pete Cooper 2bde2f42b1 Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method.
llvm-svn: 153903
2012-04-02 22:22:53 +00:00
Jakob Stoklund Olesen abe8c09b20 Make InlineSpiller bundle-aware.
Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle.  Rewrite all operands in a bundle at
once.

Don't attempt and memory operand folding inside bundles.

llvm-svn: 151787
2012-03-01 01:43:25 +00:00
Jakob Stoklund Olesen ad6b22eb16 Don't store COPY pointers in VNInfo.
If a value is defined by a COPY, that instuction can easily and cheaply
be found by getInstructionFromIndex(VNI->def).

This reduces the size of VNInfo from 24 to 16 bytes, and improves
llc compile time by 3%.

llvm-svn: 149763
2012-02-04 05:20:49 +00:00
Pete Cooper 76e4bc4e26 Fixed register allocator splitting a live range on a spilling variable.
If we create new intervals for a variable that is being spilled, then those new intervals are not guaranteed to also spill.  This means that anything reading from the original spilling value might not get the correct value if spills were missed.

Fixes <rdar://problem/10546864>

llvm-svn: 146428
2011-12-12 22:16:27 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen d7bcf43dc2 Use getVNInfoBefore() when it makes sense.
llvm-svn: 144517
2011-11-14 01:39:36 +00:00
Jakob Stoklund Olesen d8f2405e73 Terminate all dead defs at the dead slot instead of the 'next' slot.
This makes no difference for normal defs, but early clobber dead defs
now look like:

  [Slot_EarlyClobber; Slot_Dead)

instead of:

  [Slot_EarlyClobber; Slot_Register).

Live ranges for normal dead defs look like:

  [Slot_Register; Slot_Dead)

as before.

llvm-svn: 144512
2011-11-13 22:42:13 +00:00
Jakob Stoklund Olesen 90b5e565b6 Rename SlotIndexes to match how they are used.
The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

llvm-svn: 144503
2011-11-13 20:45:27 +00:00
Jakob Stoklund Olesen 28df7ef8c9 Stop tracking spill slot uses in VirtRegMap.
Nobody cared, StackSlotColoring scans the instructions to find used stack
slots.

llvm-svn: 144485
2011-11-13 01:23:30 +00:00
Jakob Stoklund Olesen eef48b6938 Strip old implicit operands after foldMemoryOperand.
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

llvm-svn: 144247
2011-11-10 00:17:03 +00:00
Jakob Stoklund Olesen 7fb5632e73 Add value numbers when spilling dead defs.
When spilling around an instruction with a dead def, remember to add a
value number for the def.

The missing value number wouldn't normally create problems since there
would be an incoming live range as well.  However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.

The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.

This fixes part of PR11125.

llvm-svn: 141923
2011-10-14 00:34:31 +00:00
Jakob Stoklund Olesen e8339b2e63 Disable local spill hoisting for non-killing copies.
If the source register is live after the copy being spilled, there is no
point to hoisting it.  Hoisting inside a basic block only serves to
resolve interferences by shortening the live range of the source.

llvm-svn: 139882
2011-09-16 00:03:33 +00:00
Jakob Stoklund Olesen bceb9e5c05 Add an option to disable spill hoisting.
When -split-spill-mode is enabled, spill hoisting is performed by
SplitKit instead of by InlineSpiller.  This hidden command line option
is for testing the splitter spill mode.

llvm-svn: 139845
2011-09-15 21:06:00 +00:00
Jakob Stoklund Olesen c94c967656 Count correctly when a COPY turns into a spill or reload.
The number of spills could go negative since a folded COPY is just a
spill, and it may be eliminated.

llvm-svn: 139815
2011-09-15 18:22:52 +00:00
Jakob Stoklund Olesen 37eb6962c6 Count inserted spills and reloads more accurately.
Adjust counters when removing spill and reload instructions.

We still don't account for reloads being removed by eliminateDeadDefs().

llvm-svn: 139806
2011-09-15 17:54:28 +00:00
Jakob Stoklund Olesen 07b3503f8b Trace through sibling PHIs in bulk.
When traceSiblingValue() encounters a PHI-def value created by live
range splitting, don't look at all the predecessor blocks.  That can be
very expensive in a complicated CFG.

Instead, consider that all the non-PHI defs jointly dominate all the
PHI-defs.  Tracing directly to all the non-PHI defs is much faster that
zipping around in the CFG when there are many PHIs with many
predecessors.

This significantly improves compile time for indirectbr interpreters.

llvm-svn: 139797
2011-09-15 16:41:12 +00:00
Jakob Stoklund Olesen 278bf02581 Reapply r139247: Cache intermediate results during traceSiblingValue.
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

The previous version had bugs that caused miscompilations. They have
been fixed.

llvm-svn: 139378
2011-09-09 18:11:41 +00:00
Jakob Stoklund Olesen 946e0a4665 Revert r139247 "Cache intermediate results during traceSiblingValue."
It broke the self host and clang-x86_64-darwin10-RA.

llvm-svn: 139259
2011-09-07 21:43:52 +00:00
Jakob Stoklund Olesen b77d5c1484 Cache intermediate results during traceSiblingValue.
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

llvm-svn: 139247
2011-09-07 19:07:31 +00:00
Jakob Stoklund Olesen e417273fce Revert r138794, "Do not try to rematerialize a value from a partial definition."
The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945
2011-09-01 17:25:18 +00:00
Bob Wilson 358a5f6a72 Do not try to rematerialize a value from a partial definition.
I don't currently have a good testcase for this; will try to get one
tomorrow.  <rdar://problem/10032939>

llvm-svn: 138794
2011-08-30 05:36:02 +00:00
Jakob Stoklund Olesen c0dd3da9c5 Fix PR10387.
When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.

Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.

Bugpoint was unable to reduce the test case for this, see PR10388.

llvm-svn: 135378
2011-07-18 05:31:59 +00:00
Jakob Stoklund Olesen 780db902f7 Oops, didn't mean to commit that.
Spills should be hoisted out of loops, but we don't want to hoist them
to dominating blocks at the same loop depth. That could cause the spills
to be executed more often.

llvm-svn: 134782
2011-07-09 01:02:44 +00:00
Jakob Stoklund Olesen bf6afec312 Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

llvm-svn: 134776
2011-07-09 00:25:03 +00:00
Jakob Stoklund Olesen bbad3bceb7 Fix PR10277.
Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

llvm-svn: 134413
2011-07-05 15:38:41 +00:00
Rafael Espindola 070f96c567 Create a isFullCopy predicate.
llvm-svn: 134189
2011-06-30 21:15:52 +00:00
Jakob Stoklund Olesen 31a0b5e2f0 Avoid hoisting spills when looking at a copy from another register that is also
about to be spilled.

This can only happen when two extra snippet registers are included in the spill,
and there is a copy between them. Hoisting the spill creates problems because
the hoist will mark the copy for later dead code elimination, and spilling the
second register will turn the copy into a spill.

<rdar://problem/9420853>

llvm-svn: 131192
2011-05-11 18:25:10 +00:00
Jakob Stoklund Olesen c5a8c08dba Add some statistics to the splitting and spilling frameworks.
llvm-svn: 130931
2011-05-05 17:22:53 +00:00
Jakob Stoklund Olesen ec9b4a6b8b Avoid using stale entries form the sibling value map.
This could happen when trying to use a value that had been eliminated after dead
code elimination and folding loads.

llvm-svn: 130597
2011-04-30 06:42:21 +00:00
Jakob Stoklund Olesen 86e53ced08 Add debug output for rematerializable instructions.
llvm-svn: 129883
2011-04-20 22:14:20 +00:00
Jakob Stoklund Olesen 9f294a9e52 Handle spilling around an instruction that has an early-clobber re-definition of
the spilled register.

This is quite common on ARM now that some stores have early-clobber defines.

llvm-svn: 129714
2011-04-18 20:23:27 +00:00
Jakob Stoklund Olesen ae044c06bf Pick a conservative register class when creating a small live range for remat.
The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.

The register class is reinflated after spilling, so the conservative choice is
only temporary.

llvm-svn: 128610
2011-03-31 03:54:44 +00:00
Jakob Stoklund Olesen e991f728d6 Recompute register class and hint for registers created during spilling.
The spill weight is not recomputed for an unspillable register - it stays infinite.

llvm-svn: 128490
2011-03-29 21:20:19 +00:00
Jakob Stoklund Olesen 0ed9ebca58 Remember to use the correct register when rematerializing for snippets.
llvm-svn: 128469
2011-03-29 17:47:02 +00:00
Jakob Stoklund Olesen add79c6abf Run dead code elimination immediately after rematerialization.
This may eliminate some uses of the spilled registers, and we don't want to
insert reloads for that.

llvm-svn: 128468
2011-03-29 17:47:00 +00:00
Jakob Stoklund Olesen d8af5298d1 Properly enable rematerialization when spilling after live range splitting.
The instruction to be rematerialized may not be the one defining the register
that is being spilled. The traceSiblingValue() function sees through sibling
copies to find the remat candidate.

llvm-svn: 128449
2011-03-29 03:12:02 +00:00
Jakob Stoklund Olesen e466345675 Use individual register classes when spilling snippets.
The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.

Use the original register class for the stack slot interval.

llvm-svn: 128351
2011-03-26 22:16:41 +00:00
Jakob Stoklund Olesen e55003fb04 Also eliminate redundant spills downstream of inserted reloads.
This can happen when multiple sibling registers are spilled after live range
splitting.

llvm-svn: 127965
2011-03-20 05:44:58 +00:00
Jakob Stoklund Olesen 39488642d3 Change an argument to a LiveInterval instead of a register number to save some redundant lookups.
llvm-svn: 127964
2011-03-20 05:44:55 +00:00