8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
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llvm-svn: 26949
2006-03-22 07:10:28 +00:00
d097e67544
Some splat and shuffle support.
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llvm-svn: 26940
2006-03-22 02:53:00 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
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- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
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llvm-svn: 26911
2006-03-21 00:33:35 +00:00
e6448448c2
Move a few things around.
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llvm-svn: 26893
2006-03-20 06:04:52 +00:00
f7c2e3628b
Vector undef's
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llvm-svn: 26870
2006-03-19 09:38:54 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
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V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
4f674921d6
Move some pattern fragments to the right files.
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llvm-svn: 26831
2006-03-17 19:55:52 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
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Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
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llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
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llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
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llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
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llvm-svn: 26300
2006-02-21 19:13:53 +00:00
Evan Cheng