f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
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llvm-svn: 37572
2007-06-13 22:20:15 +00:00
d04409154f
Added clobbersPred.
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llvm-svn: 37466
2007-06-06 10:15:28 +00:00
cc33218607
Added isPredicable bit to class Instruction.
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llvm-svn: 37117
2007-05-16 20:47:01 +00:00
d194a8603d
PredicateOperand can be used as a normal operand for isel.
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llvm-svn: 36947
2007-05-08 21:06:08 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
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feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
f65f18b2f9
expose HonorSignDependentRoundingFPMathOption to .td files
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llvm-svn: 36658
2007-05-03 00:27:11 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
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llvm-svn: 36618
2007-05-01 05:57:02 +00:00
ac9fdde7f4
Add sub-registers sets.
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llvm-svn: 36278
2007-04-20 21:13:46 +00:00
461c964d3d
Added isReMaterializable.
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llvm-svn: 35160
2007-03-19 06:22:07 +00:00
fa9227ed54
Add calling convention info
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llvm-svn: 34661
2007-02-27 06:59:52 +00:00
8c8597c4d9
Fix typos in comments.
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llvm-svn: 34456
2007-02-20 20:52:03 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
a557a0028d
Comment.
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llvm-svn: 33114
2007-01-12 07:25:16 +00:00
5c23899c7d
add a new field needed by the code emitter generator.
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llvm-svn: 31768
2006-11-15 22:55:04 +00:00
4905d2c5b4
initial steps to getting the predicate on PPC::BLR right.
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llvm-svn: 31437
2006-11-03 23:52:18 +00:00
4fcc04a32a
remove dead var
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llvm-svn: 31436
2006-11-03 23:50:15 +00:00
7a6a5b9af5
Add constraints to Instruction class.
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llvm-svn: 31332
2006-11-01 00:26:27 +00:00
adcaf294d7
Move the Imp tblgen class from the X86 backend to common code.
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llvm-svn: 30907
2006-10-12 17:49:27 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
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llvm-svn: 29193
2006-07-19 00:24:41 +00:00
f3cbd7ef31
Added a Flags field to TargetOperandInfo. Currently the only flag is
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M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.
llvm-svn: 28387
2006-05-18 20:44:26 +00:00
297e1cb10a
Remove CalleeSavedRegisters from class Target.
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llvm-svn: 28377
2006-05-18 00:09:53 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
788db2c812
Replace "../whatever.td" with "whatever.td", so that out-of-tree backends
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can just add lib/Target to TableGen includes.
llvm-svn: 28318
2006-05-16 06:39:36 +00:00
fce45ffcd6
Improve comment, patch provided by Vladimir Prus!
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llvm-svn: 28307
2006-05-15 18:35:02 +00:00
215280d8b9
Update comment.
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llvm-svn: 28283
2006-05-14 02:05:19 +00:00
85e9909755
Put PHI/INLINEASM into the correct namespace.
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llvm-svn: 28037
2006-05-01 17:00:49 +00:00
52df74000a
Renamed AddedCost to AddedComplexity.
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llvm-svn: 27843
2006-04-19 20:38:28 +00:00
aa3325e925
Allow "let AddedCost = n in" to increase pattern complexity.
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llvm-svn: 27834
2006-04-19 18:07:24 +00:00
3b338d5566
Add support for dwarf register numbering.
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llvm-svn: 27080
2006-03-24 21:13:21 +00:00
c6b13e21cc
Shuffle some includes around
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llvm-svn: 27073
2006-03-24 18:52:35 +00:00
b203355298
Split the valuetypes out of Target.td into ValueTypes.td
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llvm-svn: 26490
2006-03-03 01:55:26 +00:00
91c574b642
New type v2f32.
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llvm-svn: 26435
2006-03-01 01:06:22 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
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packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
d98701c639
Subtarget feature can now set any variable to any value
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llvm-svn: 25678
2006-01-27 08:09:42 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
7785e5b3a4
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
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hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
14c53b45f5
Added field noResults to Instruction.
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Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
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* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
d296a43f96
Added support to specify predicates.
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llvm-svn: 24715
2005-12-14 22:02:59 +00:00
e8531381e2
* Added instruction property hasCtrlDep for those which r/w control-flow
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chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
llvm-svn: 24586
2005-12-04 08:13:17 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
c418b5d938
refix typo
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llvm-svn: 24505
2005-11-29 00:42:30 +00:00
d3bc8cb26d
revert my change for the time being, which broke the build
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llvm-svn: 24503
2005-11-29 00:24:08 +00:00
50986909dc
fix a typo :)
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llvm-svn: 24501
2005-11-28 22:42:15 +00:00
252d88c68e
Capture more operand info, patch by Evan Cheng
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llvm-svn: 24422
2005-11-19 07:00:10 +00:00
227f1bdd2f
Also add the new vector value type here, for completeness.
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llvm-svn: 24405
2005-11-18 00:53:32 +00:00
53ad110490
Add attribute name and type to SubtargetFeatures.
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llvm-svn: 24012
2005-10-26 17:28:23 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
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llvm-svn: 23870
2005-10-21 19:05:19 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
Christopher Lamb