8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
...
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
621c85b038
Add AVX SSE4.1 round instructions
...
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
...
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
...
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
0ce84486c3
- Two-address pass should not assume unfolding is always successful.
...
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
llvm-svn: 107509
2010-07-02 20:36:18 +00:00
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
...
llvm-svn: 107448
2010-07-01 23:10:49 +00:00
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
...
llvm-svn: 107438
2010-07-01 22:33:18 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
...
llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
...
llvm-svn: 107308
2010-06-30 18:49:10 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
...
llvm-svn: 107306
2010-06-30 18:38:10 +00:00
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
...
llvm-svn: 107300
2010-06-30 18:06:01 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
...
llvm-svn: 107293
2010-06-30 17:03:03 +00:00
12ca3d9fac
use ArgOperand API
...
llvm-svn: 107280
2010-06-30 13:03:37 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
...
llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
...
llvm-svn: 107245
2010-06-30 03:47:56 +00:00
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
...
llvm-svn: 107243
2010-06-30 03:29:36 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
...
llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
...
llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
...
llvm-svn: 107225
2010-06-29 23:47:49 +00:00
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
...
llvm-svn: 107211
2010-06-29 22:12:16 +00:00
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
...
llvm-svn: 107206
2010-06-29 21:25:12 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
...
Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
a4575f5b31
Add AVX non-temporal stores
...
llvm-svn: 107178
2010-06-29 18:22:01 +00:00
049f4ffab1
Move non-temporal movs to their own section
...
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
...
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
67bfa9d109
Remove pointless and unused variables.
...
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
de736a6494
Refactoring of arithmetic instruction classes with unary operator
...
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
...
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
0a5bb081cc
Reduce indentation via early exit. NFC.
...
llvm-svn: 107067
2010-06-28 21:08:32 +00:00
83205af3fa
use ArgOperand API
...
llvm-svn: 106944
2010-06-26 11:51:52 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
...
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
...
llvm-svn: 106917
2010-06-25 23:47:23 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
...
llvm-svn: 106906
2010-06-25 23:04:29 +00:00
a34d9b6d84
Add several AVX MOV flavors
...
Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
...
llvm-svn: 106886
2010-06-25 21:05:35 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
...
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
...
llvm-svn: 106877
2010-06-25 20:29:27 +00:00
62d1403a03
More SSE refactoring, this time with different types of MOVs
...
llvm-svn: 106876
2010-06-25 20:22:12 +00:00
e76c0b13b9
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
...
llvm-svn: 106867
2010-06-25 18:06:22 +00:00
cbdcce6478
Add some AVX convert instructions
...
llvm-svn: 106815
2010-06-25 00:39:30 +00:00
447735aa98
Refactoring of SSE convert intrinsics
...
llvm-svn: 106808
2010-06-24 23:37:07 +00:00
78827d1952
Refactoring of SSE conversion instructions
...
llvm-svn: 106804
2010-06-24 22:22:21 +00:00
6b6b605917
Refactor SSE cmp intrinsics and declare the same for AVX
...
llvm-svn: 106796
2010-06-24 22:04:40 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
...
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
5ad5226c58
Disallow matching "i" constraint to symbol addresses when
...
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
llvm-svn: 106779
2010-06-24 20:14:51 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
...
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
...
rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
c4e84309c4
more cleanups
...
llvm-svn: 106724
2010-06-24 07:18:14 +00:00
056fd06c5f
reduce indentation
...
llvm-svn: 106723
2010-06-24 07:16:25 +00:00
c3e291c560
Fix a bug in the code which determines when it's safe to use the
...
bt instruction, which was exposed by r106263.
llvm-svn: 106718
2010-06-24 02:07:59 +00:00
fa6ce139a9
Add a couple more quick comments.
...
llvm-svn: 106717
2010-06-24 02:07:57 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
...
llvm-svn: 106705
2010-06-24 00:32:06 +00:00
6af02a6f69
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
...
llvm-svn: 106702
2010-06-24 00:15:50 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
...
llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
...
llvm-svn: 106678
2010-06-23 21:10:57 +00:00
5fed9b7c6c
Update according to feedback.
...
llvm-svn: 106677
2010-06-23 20:49:35 +00:00
360d6fe299
Add AVX SHUF{PS,PD}{rr,rm} instructions
...
llvm-svn: 106672
2010-06-23 20:07:15 +00:00
337e8db712
Add support for the x86 instructions "pusha" and "popa".
...
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
6f71039fa4
The generic DAG combiner can now fold atomic fences when needed, so switch
...
to using that.
llvm-svn: 106633
2010-06-23 16:25:07 +00:00
3d6e2c6335
Update uses, defs, and comments for darwin tls patterns.
...
llvm-svn: 106621
2010-06-23 08:01:49 +00:00
ef5a4383ad
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
...
Conflicts:
lib/CodeGen/MachineSink.cpp
llvm-svn: 106614
2010-06-23 00:48:25 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes