Bruno Cardoso Lopes
2419606bfb
Add AVX 256-bit packed MOVNT variants
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llvm-svn: 108021
2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
6bc772eec7
Add AVX 256-bit unpack and interleave
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llvm-svn: 108017
2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
Bruno Cardoso Lopes
fd8060335b
Add AVX AES instructions
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llvm-svn: 107798
2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
6d122aef97
Add AVX SSE4.2 instructions
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llvm-svn: 107752
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
3df55b2d6f
Use only one multiclass to pinsrq instructions
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llvm-svn: 107750
2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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llvm-svn: 107749
2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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llvm-svn: 107747
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
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llvm-svn: 107746
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
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llvm-svn: 107740
2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107723
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
Chris Lattner
6d60a14251
rip out even more sporadic v2f32 support.
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llvm-svn: 107610
2010-07-05 04:38:33 +00:00
Bill Wendling
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
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llvm-svn: 107585
2010-07-04 09:16:57 +00:00
Bill Wendling
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
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(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
Bruno Cardoso Lopes
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
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llvm-svn: 107560
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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llvm-svn: 107558
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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llvm-svn: 107552
2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
621c85b038
Add AVX SSE4.1 round instructions
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llvm-svn: 107549
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
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llvm-svn: 107540
2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
c7111fd355
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
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llvm-svn: 107448
2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
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llvm-svn: 107438
2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
5e88700f28
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
886ee33a38
Add AVX SSE3 packed addsub instructions
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llvm-svn: 107404
2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
a7a0c83563
Add AVX SSE3 replicate and convert instructions
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llvm-svn: 107375
2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
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llvm-svn: 107308
2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
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llvm-svn: 107306
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
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llvm-svn: 107300
2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
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llvm-svn: 107293
2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
e82689fea2
Add AVX SSE2 integer unpack instructions
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llvm-svn: 107246
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
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llvm-svn: 107245
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
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llvm-svn: 107243
2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
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llvm-svn: 107241
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
2686ea4555
Add AVX SSE2 integer packed compare instructions
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llvm-svn: 107240
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
2e2caefff9
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
3f71ddfaad
Add *several* AVX integer packed binop instructions
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llvm-svn: 107225
2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
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llvm-svn: 107211
2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
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llvm-svn: 107206
2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
30689a3a7f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
a4575f5b31
Add AVX non-temporal stores
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llvm-svn: 107178
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
049f4ffab1
Move non-temporal movs to their own section
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llvm-svn: 107168
2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
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llvm-svn: 107166
2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
de736a6494
Refactoring of arithmetic instruction classes with unary operator
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llvm-svn: 107116
2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
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llvm-svn: 107108
2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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llvm-svn: 106917
2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
83651094ad
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
4530fed87e
revert this now, it's using avx instead of sse :)
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llvm-svn: 106906
2010-06-25 23:04:29 +00:00