2022c79d7f
Added properties such as SDNPHasChain to ComplexPattern.
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llvm-svn: 30890
2006-10-11 21:02:01 +00:00
5d038cf802
Allow more use of iPTR in patterns.
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llvm-svn: 28790
2006-06-15 00:16:37 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
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llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
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llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
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represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
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register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
989b16e488
Fix a typo: Instr* -> Intr*
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llvm-svn: 27568
2006-04-10 22:02:59 +00:00
8a2ae8b766
Only compute intrinsic valuetypes when in a target .td file.
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llvm-svn: 27197
2006-03-28 00:15:00 +00:00
ac2512a261
revert this, it breaks things.
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llvm-svn: 27196
2006-03-28 00:03:08 +00:00
c92f688ef3
Add support for decoding iPTR to the right pointer type.
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llvm-svn: 27188
2006-03-27 22:48:18 +00:00
bbba823706
Make sure to initialize the TheDef field!
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llvm-svn: 27078
2006-03-24 20:25:01 +00:00
2c58141fd9
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
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the CodeGen* implementations.
Parse the MVT::ValueType for each operand of the intrinsics.
llvm-svn: 27075
2006-03-24 19:49:31 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
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llvm-svn: 26869
2006-03-19 07:57:34 +00:00
53a2d60bca
New vector type v2f32.
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llvm-svn: 26437
2006-03-01 01:10:52 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
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packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
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llvm-svn: 25673
2006-01-27 01:45:06 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
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SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
14c53b45f5
Added field noResults to Instruction.
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Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
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support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
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llvm-svn: 24753
2005-12-17 01:19:28 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
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* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
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matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
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* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
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llvm-svn: 24556
2005-12-01 00:12:04 +00:00
4d0251ad55
Add the new vector types to tablegen
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llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
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to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
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operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
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reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
90c5b9c83c
Do not let getLegalValueTypes return a list with duplicates in it
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llvm-svn: 23723
2005-10-14 03:54:49 +00:00
3ced3f8b82
force all instruction operands to be named.
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llvm-svn: 23358
2005-09-14 21:13:50 +00:00
f02994d782
Check that operands have unique names. REJECT instructions with broken operand
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lists: only don't parse them if they are entirely missing (sparcv9).
llvm-svn: 23355
2005-09-14 21:05:02 +00:00
ae939eb6bb
Add a new Record::getValueAsCode method to mirror the other getValueAs*
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methods. Use it to simplify some code.
llvm-svn: 23336
2005-09-13 21:44:28 +00:00
cee994b464
Compute the value types that are natively supported by a target.
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llvm-svn: 23282
2005-09-08 21:43:21 +00:00
c6a0338c04
spell this right
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llvm-svn: 23099
2005-08-26 20:55:40 +00:00
63dc7f569a
spell this variable right
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llvm-svn: 23095
2005-08-26 20:42:52 +00:00
3d9fbefbf7
Expose a new flag to TargetInstrInfo
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llvm-svn: 23094
2005-08-26 20:40:46 +00:00
73ec2cb0f5
Split register class "Methods" into MethodProtos and MethodBodies
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llvm-svn: 22928
2005-08-19 19:12:51 +00:00
418d8cfcfe
Read the namespace field from register classes
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llvm-svn: 22918
2005-08-19 18:45:20 +00:00
0899614152
Fix a problem jeffc noticed
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llvm-svn: 22903
2005-08-19 06:16:04 +00:00
17727bad02
Figure out how many operands each instruction has, keep track of whether
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or not it's variable.
llvm-svn: 22885
2005-08-18 23:38:41 +00:00
650ba8eb56
Remove trailing whitespace
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llvm-svn: 21428
2005-04-22 00:00:37 +00:00
945e8655dd
Refactor code for numbering instructions into CodeGenTarget.
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llvm-svn: 19758
2005-01-22 18:58:51 +00:00
733c82bfbf
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
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llvm-svn: 19243
2005-01-02 02:29:04 +00:00
243ded5e1a
* Add option to read isLittleEndianEncoding for InstrInfo classes
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* Doxygen-ify some function comments
llvm-svn: 16974
2004-10-14 05:50:43 +00:00
91c538f2a1
Add initial support for variants. This just parses the new format, no
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functionality is added
llvm-svn: 16636
2004-10-03 19:34:31 +00:00
996ddbc98e
Add support for the isLoad and isStore flags, needed by the instruction scheduler
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llvm-svn: 16554
2004-09-28 21:01:45 +00:00
9b0dfa3c0d
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
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llvm-svn: 16553
2004-09-28 18:38:01 +00:00
8eab62ee0d
Alignment is now in bits.
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llvm-svn: 15976
2004-08-21 20:15:25 +00:00
beadefde19
Make alignment be in bits, just like size is
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llvm-svn: 15969
2004-08-21 20:00:36 +00:00
d3244d9cec
Support "Methods" in register classes in CodgeGenRegisterClass
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llvm-svn: 15965
2004-08-21 19:21:21 +00:00
2a86fab933
Start parsing register classes into a more structured form
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llvm-svn: 15961
2004-08-21 04:05:00 +00:00
e34ae99942
Read in declared reg sizes
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llvm-svn: 15960
2004-08-21 02:24:57 +00:00
8af61ddb96
Use CodeGenRegister class to make reading in of register information more
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systematic.
llvm-svn: 15805
2004-08-16 01:10:21 +00:00
6ffa501d9f
Make the AsmWriter a first-class tblgen object. Allow targets to specify
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name of the generated asmwriter class, and the name of the format string.
llvm-svn: 15747
2004-08-14 22:50:53 +00:00
3bc477a237
Start parsing more information from the Operand information
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llvm-svn: 15644
2004-08-11 02:22:39 +00:00
101f3fea82
Remove special case hacks
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llvm-svn: 15643
2004-08-11 01:53:58 +00:00
5572682faa
Parse the operand list of the instruction. We currently support register and immediate operands.
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llvm-svn: 15390
2004-08-01 07:42:39 +00:00
1c4ae85035
Initial cut at an asm writer emitter. So far, this only handles emission of
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instructions, and only instructions that take no operands at that!
llvm-svn: 15386
2004-08-01 05:59:33 +00:00
c860ecafe1
Add, and start using, the CodeGenInstruction class. This class represents
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an instance of the Instruction tablegen class.
llvm-svn: 15385
2004-08-01 05:04:00 +00:00
fce9603387
Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
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llvm-svn: 15382
2004-08-01 04:04:35 +00:00
Evan Cheng