Commit Graph

3428 Commits

Author SHA1 Message Date
Joerg Sonnenberger 302be7e891 Fix spelling.
llvm-svn: 207982
2014-05-05 17:58:46 +00:00
Rafael Espindola 665bd05095 Move test to the ARM64 directory.
llvm-svn: 207972
2014-05-05 16:14:37 +00:00
Rafael Espindola f463b63448 Convert a CodeGen test into a MC test.
llvm-svn: 207971
2014-05-05 15:34:13 +00:00
Saleem Abdulrasool 729c7a08fb MC: support FK_SecRel_4 for Windows on ARM
Add handling for FK_SecRel_4 (4-byte section relative relocations).  These are
used by the generation of DWARF debug information (the abbrevations use section
relative relocations).  This will also be used in generation of CodeView line
tables.

llvm-svn: 207941
2014-05-04 23:13:15 +00:00
Rafael Espindola 3d082fa507 Fix pr19645.
The fix itself is fairly simple: move getAccessVariant to MCValue so that we
replace the old weak expression evaluation with the far more general
EvaluateAsRelocatable.

This then requires that EvaluateAsRelocatable stop when it finds a non
trivial reference kind. And that in turn requires the ELF writer to look
harder for weak references.

Last but not least, this found a case where we were being bug by bug
compatible with gas and accepting an invalid input. I reported pr19647
to track it.

llvm-svn: 207920
2014-05-03 19:57:04 +00:00
Saleem Abdulrasool 734bca04ff MC: place .file records into the correct section
.file records are supposed to have a section identifier of 65534
(IMAGE_SCN_DEBUG) rather than 0.  This is spelt out clearly within the PE/COFF
specification.  Fix this minor oversight with the implementation for support for
.file records.

llvm-svn: 207851
2014-05-02 17:45:24 +00:00
Rafael Espindola ea9f9d4030 Don't propagate StorageClass and ComplexType to aliases.
This matches gas' behaviour on COFF.

I think that this yak is now sufficiently shaved for aliases with offset
to work.

llvm-svn: 207786
2014-05-01 19:02:03 +00:00
Rafael Espindola 575f79a409 Compute the correct section for zed = foo + 1 in COFF.
This fixes pr19147.

There are a few more related issues to fix, but the testcase in the bug now
passes.

llvm-svn: 207763
2014-05-01 13:37:57 +00:00
Rafael Espindola 4a04294882 Don't force symbols to be globals in .thumb_set.
We currently force symbols to be globals in .thumb_set. The intent
seems to be that given

.thumb_set foo, bar

we emit an undefined symbol to bar if it is never defined. The side
effect is that we mark bar as global, even if it is defined, which gas
does not.

Producing an undefined reference to bar is a general difference from MC and gas.
For example, given

a = b

gas will produce an undefined reference to b, MC will not. I would be surprised
if any code depends on this, but it it does, we should fix the general
difference, not special case .thumb_set.

llvm-svn: 207757
2014-05-01 12:45:43 +00:00
Tim Northover 05017b1f8c AArch64/ARM64: rewrite test to use FileCheck & add ARM64 lines
llvm-svn: 207754
2014-05-01 12:30:01 +00:00
Tim Northover 4ec135fa2e AArch64/ARM64: port basic disassembly tests to ARM64.
llvm-svn: 207753
2014-05-01 12:29:56 +00:00
Tim Northover 534acbdf73 AArch64/ARM64: print BFM instructions as BFI or BFXIL
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

llvm-svn: 207752
2014-05-01 12:29:38 +00:00
Richard Barton 3db1d580b3 Correction to assert statemtent to allow 32-bit unsigned numbers with the top bit set.
This fixes an ARM assembler crash - regression test added.

llvm-svn: 207747
2014-05-01 11:37:44 +00:00
Bradley Smith f57d5ca234 [ARM64] Conditionalize CPU specific system registers on subtarget features
llvm-svn: 207742
2014-05-01 10:25:36 +00:00
Matheus Almeida d92a3fa212 [mips] Move expansion of .cpsetup to target streamer.
Summary:
There are two functional changes:
1) The directive is not expanded for the ASM->ASM code path.
2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3482

llvm-svn: 207741
2014-05-01 10:24:46 +00:00
Daniel Sanders 88fbbcaa30 [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, and drotrv
GAS doesn't actually accept these particular cases.

The mnemonic without the trailing 'v' still supports two-operand aliases.

llvm-svn: 207740
2014-05-01 10:08:36 +00:00
Oliver Stannard 7eacbd5a71 Record the DWARF version in MCContext
Record the DWARF version in MCContext, and use it when
emitting the dwarf version into the debug info.

llvm-svn: 207739
2014-05-01 08:46:02 +00:00
Rafael Espindola ff68cb7f4c Start fixing pr19147.
This makes the coff writer compute the correct symbol value for the test in
pr19147. The section is still incorrect, that will be fixed in a followup patch.

llvm-svn: 207728
2014-05-01 00:10:17 +00:00
James Molloy cbb9791e3b Move a testcase from ELF to ARM64, incorrectly placed in r207627.
llvm-svn: 207706
2014-04-30 21:31:11 +00:00
James Molloy 3ef43692b4 Add a testcase for r207627.
llvm-svn: 207697
2014-04-30 20:06:26 +00:00
Matheus Almeida e844872830 [mips] Add instruction alias (negu).
Summary: negu $reg is equivalent to negu $reg, $reg.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3510

llvm-svn: 207673
2014-04-30 16:53:49 +00:00
Matheus Almeida b7be52343d [mips] Add instruction alias (sltu).
Summary:
The pattern sltu $r1, $r2, $imm is found in handwritten assembly which
is just a shorthand version of sltui $r1, $r2, $imm.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3508

llvm-svn: 207671
2014-04-30 16:29:56 +00:00
Hans Wennborg 83e6e1e926 ELFObjectWriter: deduplicate suffices in strtab
We already do this for shstrtab, so might as well do it for strtab. This
extracts the string table building code into a separate class. The idea
is to use it for other object formats too.

I mostly wanted to do this for the general principle, but it does save a
little bit on object file size. I tried this on a clang bootstrap and
saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for
a release build).

Differential Revision: http://reviews.llvm.org/D3533

llvm-svn: 207670
2014-04-30 16:25:02 +00:00
Tim Northover a8c577e454 ARM64: print fp immediates without using scientific notation.
llvm-svn: 207669
2014-04-30 16:13:34 +00:00
Tim Northover 7346f062b6 AArch64/ARM64: implement remaining TLS relocations (purely MC).
llvm-svn: 207668
2014-04-30 16:13:26 +00:00
Tim Northover b8fb7f4193 AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.
llvm-svn: 207667
2014-04-30 16:13:20 +00:00
Tim Northover 3c9a9401d5 AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"
It's been decided that in the future, the floating-point immediate in
instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which
has been implemented on AArch64 already but not ARM64.

This fixes that issue.

llvm-svn: 207666
2014-04-30 16:13:07 +00:00
Matheus Almeida 56df6ff2c5 [mips] Add instruction alias (dsll and dsrl).
Summary:
The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3486

llvm-svn: 207664
2014-04-30 16:00:49 +00:00
Rafael Espindola b36f6189a5 Relax the test a bit.
It is not relevant where the symbol and section names are stored, just their
values.

llvm-svn: 207662
2014-04-30 15:32:21 +00:00
Rafael Espindola 194924e64b Rename the test, it is testing the symver directive.
llvm-svn: 207658
2014-04-30 15:27:44 +00:00
Matheus Almeida 312ac02491 [mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3483

llvm-svn: 207657
2014-04-30 15:23:04 +00:00
Matheus Almeida bbd5e85e21 [mips] Update tests with encoding information for slt, slti, sltiu and sltu.
Summary:
Also renamed non-portable register names (e.g. $t2) so that we don't end up
with a different encoding for what appears to be an equivalent instruction.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3505

llvm-svn: 207655
2014-04-30 14:52:57 +00:00
Tim Northover 3ffee2340e ARM64: enable AArch64's basic-a64-instructions test
llvm-svn: 207650
2014-04-30 13:37:10 +00:00
Tim Northover 0ac99404f0 ARM64: print lsr instead of lsrv for variable shifts (etc)
The canonical syntax for shifts by a variable amount does not end with 'v', but
that syntax should be supported as an alias (presumably for legacy reasons).

llvm-svn: 207649
2014-04-30 13:37:07 +00:00
Tim Northover 7030f05b4f ARM64: use 32-bit operations for uxtb & uxth
Testing will be enabled shortly with basic-a64-instructions.s

llvm-svn: 207648
2014-04-30 13:37:02 +00:00
Tim Northover a307769b15 AArch64/ARM64: copy support for bCC instead of b.CC across.
llvm-svn: 207646
2014-04-30 13:36:56 +00:00
Tim Northover 20ad359b77 AArch64/ARM64: use HS instead of CS & LO instead of CC.
On instructions using the NZCV register, a couple of conditions have dual
representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and
unsigned-lower/carry-clear). The first of these is more descriptive in most
circumstances, so we should print it.

llvm-svn: 207644
2014-04-30 13:14:03 +00:00
Tim Northover f9941a9dc6 ARM64: accept ELF-relocated load/store insts without a #.
E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax
too.

llvm-svn: 207639
2014-04-30 12:00:20 +00:00
Matheus Almeida 525bc4f708 [mips] Add support for .cpload.
Summary:
This directive is used for setting up $gp in the beginning of a function.
It expands to three instructions if PIC is enabled:
lui   $gp, %hi(_gp_disp)
addui $gp, $gp, %lo(_gp_disp)
addu  $gp, $gp, $reg

_gp_disp is a special symbol that the linker sets to the distance between
the lui instruction and the context pointer (_gp).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3480

llvm-svn: 207637
2014-04-30 11:28:42 +00:00
Matheus Almeida c0284d118f [mips] Emit all three relocation operations for each relocation entry on Mips64 big-endian systems.
Summary:
The N64 ABI allows up to three operations to be specified per relocation record
independently of the endianness.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3529

llvm-svn: 207636
2014-04-30 11:21:10 +00:00
Tim Northover 970c4a8d35 ARM64: use hex immediates for movz/movk instructions
Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

llvm-svn: 207635
2014-04-30 11:19:40 +00:00
Tim Northover 4b2f8a990e ARM64: hexify printing various immediate operands
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

llvm-svn: 207634
2014-04-30 11:19:28 +00:00
Tim Northover cfd6e66544 ARM64: print canonical syntax for add/sub (imm) instructions.
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

llvm-svn: 207633
2014-04-30 11:19:15 +00:00
Saleem Abdulrasool 0aca1c30c6 ARM: print COFF function header for Windows on ARM
Emit the COFF header when printing out the function.  This is important as the
header contains two important pieces of information: the storage class for the
symbol and the symbol type information.  This bit of information is required for
the linker to correctly identify the type of symbol that it is dealing with.

llvm-svn: 207613
2014-04-30 06:14:25 +00:00
Joerg Sonnenberger dd18d5b0f6 Parse and create GOT_PREL relocations.
llvm-svn: 207526
2014-04-29 13:42:02 +00:00
Rafael Espindola b60c829a2a Centralize the handling of the thumb bit.
This patch centralizes the handling of the thumb bit around
MCStreamer::isThumbFunc and makes isThumbFunc handle aliases.

This fixes a corner case, but the main advantage is having just one
way to check if a MCSymbol is thumb or not. This should still be
refactored to be ARM only, but at least now it is just one predicate
that has to be refactored instead of 3 (isThumbFunc,
ELF_Other_ThumbFunc, and SF_ThumbFunc).

llvm-svn: 207522
2014-04-29 12:46:50 +00:00
Rafael Espindola bc91d7e25a Add an option for evaluating past symbols.
When evaluating an assembly expression for a relocation, we want to
stop at MCSymbols that are in the symbol table, even if they are variables.
This is needed since the semantics may require that the relocation use them.

That is not the case when computing the value of a symbol in the symbol table.
There are no relocations in this case and we have to keep going until we hit
a section or find out that the expression doesn't have an assembly time
value.

llvm-svn: 207445
2014-04-28 20:53:11 +00:00
Rafael Espindola 3b5ee55804 Don't include an invalid symbol in the symbol table.
The symbol table itself has no relocations, so it is not possible to represent
things like

a = undefined + 1

With the patch we just omit these variables. That matches the behaviour of the
gnu assembler.

llvm-svn: 207419
2014-04-28 13:39:57 +00:00
Rafael Espindola 407f5be3cc List the entire symbol table in this test.
This will allow us to extend this test to show that other symbols don't
show up in the symbol table.

llvm-svn: 207418
2014-04-28 13:26:35 +00:00
Rafael Espindola 9645090181 Produce an error instead of a crash in an expr we cannot represent.
llvm-svn: 207414
2014-04-28 12:40:50 +00:00