Commit Graph

722 Commits

Author SHA1 Message Date
Jim Ingham 8d543de400 Remove unneeded ExecutionContextScope variables.
llvm-svn: 128685
2011-03-31 23:01:21 +00:00
Caroline Tice d20c8d1a17 Fix a few typos in the previous commit.
llvm-svn: 128671
2011-03-31 21:31:50 +00:00
Caroline Tice 028b8b7bb7 Add code to emulate VLD1 (single element to all lanes) ARM instruction.
llvm-svn: 128669
2011-03-31 21:15:29 +00:00
Caroline Tice 5901ea7e67 Add code to emulate VST1 (single element from one lane) ARM
instruction (more floating point stores).

llvm-svn: 128661
2011-03-31 19:17:12 +00:00
Caroline Tice d64a08144c Add code to emulate VST1 (multiple single elements) ARM
instruction (floating point store).

llvm-svn: 128656
2011-03-31 18:44:04 +00:00
Caroline Tice bc2b96b699 Add code to emulate VLD1 (single element to one lane) floating point
register load instruction (ARM) .

llvm-svn: 128646
2011-03-31 17:58:23 +00:00
Caroline Tice 31d8498f6f Add code to emulate VLD1 (multiple single elements) ARM instruction.
llvm-svn: 128637
2011-03-31 16:41:19 +00:00
Caroline Tice 8e4ed85520 Add code to emulate VSTR ARM instruction (store a floating point register).
llvm-svn: 128614
2011-03-31 05:38:36 +00:00
Caroline Tice df6dec754b Add code to emulate the VLDR Arm instruction (load a floating poitn register).
llvm-svn: 128613
2011-03-31 05:05:30 +00:00
Caroline Tice b5c6a3e50a Add "Bits64" utility function.
Add code to emulate VSTM ARM instruction (store multiple floating point registers).

llvm-svn: 128609
2011-03-31 03:26:23 +00:00
Greg Clayton 05d2b7f741 Added some functions to our API related to classifying symbols as code, data,
const data, etc, and also for SBAddress objects to classify their type of
section they are in and also getting the module for a section offset address.

    lldb::SymbolType SBSymbol::GetType();
    
    lldb::SectionType SBAddress::GetSectionType ();
    lldb::SBModule SBAddress::GetModule ();

llvm-svn: 128602
2011-03-31 01:08:07 +00:00
Caroline Tice 920c6c9855 Modify ARM instruction tables to allow for specifying floating point variants.
Add code to emulate VLDM ARM instruction (loading multiplt floating point registers).

Add function declarations for other floating point instructions to emulate.

llvm-svn: 128589
2011-03-31 00:02:51 +00:00
Caroline Tice 55bff33b50 Fill in code for EmulateSTRDImm and EmulateSTRDReg, to emulate the
STRD (immediate) and STRD (register) instructions.

llvm-svn: 128570
2011-03-30 19:02:56 +00:00
Greg Clayton 32e0a7509c Many improvements to the Platform base class and subclasses. The base Platform
class now implements the Host functionality for a lot of things that make 
sense by default so that subclasses can check:

int
PlatformSubclass::Foo ()
{
    if (IsHost())
        return Platform::Foo (); // Let the platform base class do the host specific stuff
    
    // Platform subclass specific code...
    int result = ...
    return result;
}

Added new functions to the platform:

    virtual const char *Platform::GetUserName (uint32_t uid);
    virtual const char *Platform::GetGroupName (uint32_t gid);

The user and group names are cached locally so that remote platforms can avoid
sending packets multiple times to resolve this information.

Added the parent process ID to the ProcessInfo class. 

Added a new ProcessInfoMatch class which helps us to match processes up
and changed the Host layer over to using this new class. The new class allows
us to search for processs:
1 - by name (equal to, starts with, ends with, contains, and regex)
2 - by pid
3 - And further check for parent pid == value, uid == value, gid == value, 
    euid == value, egid == value, arch == value, parent == value.
    
This is all hookup up to the "platform process list" command which required
adding dumping routines to dump process information. If the Host class 
implements the process lookup routines, you can now lists processes on 
your local machine:

machine1.foo.com % lldb
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari
94727  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Xcode
92742  92710  username   usergroup  username   usergroup  i386-apple-darwin        debugserver


This of course also works remotely with the lldb-platform:

machine1.foo.com % lldb-platform --listen 1234

machine2.foo.com % lldb
(lldb) platform create remote-macosx
  Platform: remote-macosx
 Connected: no
(lldb) platform connect connect://localhost:1444
  Platform: remote-macosx
    Triple: x86_64-apple-darwin
OS Version: 10.6.7 (10J869)
    Kernel: Darwin Kernel Version 10.7.0: Sat Jan 29 15:17:16 PST 2011; root:xnu-1504.9.37~1/RELEASE_I386
  Hostname: machine1.foo.com
 Connected: yes
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99556  244    username   usergroup  username   usergroup  x86_64-apple-darwin      trustevaluation
99548  65539  username   usergroup  username   usergroup  x86_64-apple-darwin      lldb
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari

The lldb-platform implements everything with the Host:: layer, so this should
"just work" for linux. I will probably be adding more stuff to the Host layer
for launching processes and attaching to processes so that this support should
eventually just work as well.

Modified the target to be able to be created with an architecture that differs
from the main executable. This is needed for iOS debugging since we can have
an "armv6" binary which can run on an "armv7" machine, so we want to be able
to do:

% lldb
(lldb) platform create remote-ios
(lldb) file --arch armv7 a.out

Where "a.out" is an armv6 executable. The platform then can correctly decide
to open all "armv7" images for all dependent shared libraries.

Modified the disassembly to show the current PC value. Example output:

(lldb) disassemble --frame
a.out`main:
   0x1eb7:  pushl  %ebp
   0x1eb8:  movl   %esp, %ebp
   0x1eba:  pushl  %ebx
   0x1ebb:  subl   $20, %esp
   0x1ebe:  calll  0x1ec3                   ; main + 12 at test.c:18
   0x1ec3:  popl   %ebx
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf
   0x1edb:  leal   213(%ebx), %eax
   0x1ee1:  movl   %eax, (%esp)
   0x1ee4:  calll  0x1f1e                   ; puts
   0x1ee9:  calll  0x1f0c                   ; getchar
   0x1eee:  movl   $20, (%esp)
   0x1ef5:  calll  0x1e6a                   ; sleep_loop at test.c:6
   0x1efa:  movl   $12, %eax
   0x1eff:  addl   $20, %esp
   0x1f02:  popl   %ebx
   0x1f03:  leave
   0x1f04:  ret
   
This can be handy when dealing with the new --line options that was recently
added:

(lldb) disassemble --line
a.out`main + 13 at test.c:19
   18  	{
-> 19  		printf("Process: %i\n\n", getpid());
   20  	    puts("Press any key to continue..."); getchar();
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf

Modified the ModuleList to have a lookup based solely on a UUID. Since the
UUID is typically the MD5 checksum of a binary image, there is no need
to give the path and architecture when searching for a pre-existing
image in an image list.

Now that we support remote debugging a bit better, our lldb_private::Module
needs to be able to track what the original path for file was as the platform
knows it, as well as where the file is locally. The module has the two 
following functions to retrieve both paths:

const FileSpec &Module::GetFileSpec () const;
const FileSpec &Module::GetPlatformFileSpec () const;

llvm-svn: 128563
2011-03-30 18:16:51 +00:00
Caroline Tice 23443245e7 Fill in EmulateLDRDRegister to emulate LDRD (register) instruction.
Remove stubs for functions not-to-be-implemented at the moment.

llvm-svn: 128559
2011-03-30 17:54:52 +00:00
Caroline Tice f0901227e3 Fill in EmulateLDRLImmediate to emulate the LDRD (immediate) ARM instruction.
llvm-svn: 128556
2011-03-30 17:11:45 +00:00
Stephen Wilson 464280542b linux: create thread plans for stepping thru PLT entries
Using the new synthetic symbols generated by ObjectFileELF, have the Linux
dynamic loader plugin generate a thread plan that will take us thru a PLT entry
to the corresponding target function.

llvm-svn: 128552
2011-03-30 16:11:36 +00:00
Stephen Wilson 499b40e8a7 elf: synthesize symbols for PLT entries
When populating symbol tables ObjectFileELF now generates a set of synthetic
trampoline symbols.  These new symbols correspond to entries in the program
linkage table and have a (possibly mangled) name identifying the corresponding
symbol in some DSO.  These symbols will be used by the DynamicLoader loader
plugin on Linux to provide thread plans when execution flows from one DSO to
another.

llvm-svn: 128550
2011-03-30 16:07:05 +00:00
Caroline Tice e746dbf83b Fix typo in previous check-in.
llvm-svn: 128549
2011-03-30 16:05:23 +00:00
Stephen Wilson 43fe645b62 elf: add support for ELF relocation entries
llvm-svn: 128548
2011-03-30 15:59:12 +00:00
Stephen Wilson 84ffe7033c linux: initial support for 'real' signal handling
This patch upgrades the Linux process plugin to handle a larger range of signal
events.  For example, we can detect when the inferior has "crashed" and why,
interrupt a running process, deliver an arbitrary signal, and so on.

llvm-svn: 128547
2011-03-30 15:55:52 +00:00
Caroline Tice 527637d64a Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction.
llvm-svn: 128528
2011-03-30 06:03:24 +00:00
Caroline Tice a0e8cd5e89 Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.
llvm-svn: 128527
2011-03-30 05:40:56 +00:00
Caroline Tice 4cee4bd9f4 Fill in EmulateSTREX to emulate the STREX ARM instruction.
llvm-svn: 128525
2011-03-30 05:15:46 +00:00
Stephen Wilson dc91686f48 Unfortunately, sranddev() is not available on all platforms so seed using the
current time instead.

llvm-svn: 128514
2011-03-30 00:12:40 +00:00
Caroline Tice 799e203894 Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction.
llvm-svn: 128508
2011-03-29 23:44:20 +00:00
Caroline Tice c5bcda4619 Fill in code in EmulateADDRegShift, to emulate the ADD
(register-shifted register) ARM instruction.

llvm-svn: 128500
2011-03-29 23:03:16 +00:00
Jim Ingham 7572fa75cf Can't just call "rand" to get a random port, 'cause then you'll get the same sequence in two lldb's. This makes running lldb on lldb not work very well.
llvm-svn: 128493
2011-03-29 21:45:47 +00:00
Caroline Tice eba8f83479 Add subtraction context.
Add code to emulate SUB (SP minus register) ARM instruction.

Add stubs for other ARM emulation functions that need to be written.

llvm-svn: 128491
2011-03-29 21:24:06 +00:00
Caroline Tice 3f0bfdacc1 Add missing encodings for EmulateMOVRdImm (MOV register) function.
llvm-svn: 128479
2011-03-29 19:53:44 +00:00
Caroline Tice 87c19f61d4 Fix single quote characters throughout the ARM emulation stuff.
Fix bugs in various ARM istruction emulation functions:

EmulateVPUSH
   - Fix context.
   - Fix bug calculating register numbers.

EmulateVPOP
   - Fix context.
   - Fix bug calculating register numbers.

EmulateShiftIMM
   - Fix bug in assert statement.

EmulateLDMDA
   - Fix context.

EmulateLDMDB
   - Fix context.

EmulateLDMIB
   - Fix context.     

EmulateSTM
   - Fix bug calculating lowest_set_bit.     

EmulateSTMDA
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMDB
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMIB
   - FIx context     

EmulateLDRSBImmed
   - Fix test to match correction in corrected manual 

llvm-svn: 128409
2011-03-28 16:10:45 +00:00
Greg Clayton 357132eb9a Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:

uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;

uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;

Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than 
once.

Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.

Changed:

	bool
	SymbolContextList::AppendIfUnique (const SymbolContext& sc);

To:
	bool
	SymbolContextList::AppendIfUnique (const SymbolContext& sc, 
									   bool merge_symbol_into_function);

This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.

Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").

Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump 
them and show the opcode bytes, we can format the output more 
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.

Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported 
architecture. I also added the ability to specify "thumb" as an 
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:

(lldb) disassemble --arch thumb --name main

You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080:  0xb580 push   {r7, lr}
0x100001082:  0xaf00 add    r7, sp, #0

Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.

llvm-svn: 128347
2011-03-26 19:14:58 +00:00
Stephen Wilson 78decfd025 linux: minor updates to account for recent namespace changes
llvm-svn: 128313
2011-03-26 00:34:57 +00:00
Stephen Wilson 63f37bba1a Add PlatformGDBServer and ProcessGDBRemote to the build system.
llvm-svn: 128312
2011-03-26 00:32:59 +00:00
Stephen Wilson a78867b899 Simple fixes for the gdb remote process plugin on Linux.
llvm-svn: 128291
2011-03-25 18:16:28 +00:00
Greg Clayton 1080edbcdd Cleaned up the Disassembler code a bit more. You can now request a disassembler
plugin by name on the command line for when there is more than one disassembler
plugin.

Taught the Opcode class to dump itself so that "disassembler -b" will dump
the bytes correctly for each opcode type. Modified all places that were passing
the opcode bytes buffer in so that the bytes could be displayed to just pass
in a bool that indicates if we should dump the opcode bytes since the opcode
now lives inside llvm_private::Instruction.

llvm-svn: 128290
2011-03-25 18:03:16 +00:00
Greg Clayton 0ae962735f Made the lldb_private::Opcode struct into a real boy... I mean class.
Modified the Disassembler::Instruction base class to contain an Opcode 
instance so that we can know the bytes for an instruction without needing
to keep the data around.

Modified the DisassemblerLLVM's instruction class to correctly extract the
opcode bytes if all goes well.

llvm-svn: 128248
2011-03-24 23:53:38 +00:00
Greg Clayton e0d378b334 Fixed the LLDB build so that we can have private types, private enums and
public types and public enums. This was done to keep the SWIG stuff from
parsing all sorts of enums and types that weren't needed, and allows us to
abstract our API better.

llvm-svn: 128239
2011-03-24 21:19:54 +00:00
Caroline Tice 466327d604 Fix small bug in ThumbExpandImm_C; arguments to a call to 'bits' were
in the wrong order.

llvm-svn: 128237
2011-03-24 21:11:26 +00:00
Caroline Tice 9b281e2214 Add missing encodings for EmulateLDRRtRnImm (ARM insn emulation funciton).
llvm-svn: 128229
2011-03-24 19:23:45 +00:00
Greg Clayton 1cb6496eb0 Did a lot more work on abtracting and organizing the platforms.
On Mac OS X we now have 3 platforms:
PlatformDarwin - must be subclassed to fill in the missing pure virtual funcs
                 but this implements all the common functionality between
                 remote-macosx and remote-ios. It also allows for another
                 platform to be used (remote-gdb-server for now) when doing
                 remote connections. Keeping this pluggable will allow for
                 flexibility.
PlatformMacOSX - Now implements both local and remote macosx desktop platforms.
PlatformRemoteiOS - Remote only iOS that knows how to locate SDK files in the
                    cached SDK locations on the host.

A new agnostic platform has been created:
PlatformRemoteGDBServer - this implements the platform using the GDB remote 
                          protocol and uses the built in lldb_private::Host
                          static functions to implement many queries.

llvm-svn: 128193
2011-03-24 04:28:38 +00:00
Stephen Wilson 26977167bc linux: simple support for process input and output
llvm-svn: 128137
2011-03-23 02:14:42 +00:00
Stephen Wilson ecc114745e linux: PlatformLinux improvements
Add a few missing virtual methods to PlatformLinux and have it register itself
with PluginManager.

llvm-svn: 128128
2011-03-23 00:57:47 +00:00
Greg Clayton d314e810a7 Added new platform commands:
platform connect <args>
platform disconnect

Each platform can decide the args they want to use for "platform connect". I 
will need to add a function that gets the connect options for the current
platform as each one can have different options and argument counts.

Hooked up more functionality in the PlatformMacOSX and PlatformRemoteiOS.
Also started an platform agnostic PlatformRemoteGDBServer.cpp which can end
up being used by one or more actual platforms. It can also be specialized and
allow for platform specific commands.

llvm-svn: 128123
2011-03-23 00:09:55 +00:00
Caroline Tice 3e1fa1ad09 More fixes for ARM instruction emulation code:
- Remove duplicate write from EmulateLDRRtPCRelative.
  - Add a missing encoding to EmulateADDSPImm.
  - Fix minor problems in Thumb instruction tables.

llvm-svn: 128115
2011-03-22 22:38:28 +00:00
Greg Clayton 576d8834fe Split the GDBRemoteCommunication class into three classes:
GDBRemoteCommunication - The base GDB remote communication class
GDBRemoteCommunicationClient - designed to be used for clients the connect to
                               a remote GDB server
GDBRemoteCommunicationServer - designed to be used on the server side of a
                               GDB server implementation.

llvm-svn: 128070
2011-03-22 04:00:09 +00:00
Jim Ingham 37023b06bd Add the ability to disassemble "n" instructions from the current PC, or the first "n" instructions in a function.
Also added a "-p" flag that disassembles from the current pc.

llvm-svn: 128063
2011-03-22 01:48:42 +00:00
Greg Clayton 7a5388bf75 Split all of the core of LLDB.framework/lldb.so into a
static archive that can be linked against. LLDB.framework/lldb.so
exports a very controlled API. Splitting the API into a static
library allows other tools (debugserver for now) to use the power
of the LLDB debugger core, yet not export it as its API is not
portable or maintainable. The Host layer and many of the other
internal only APIs can now be statically linked against.

Now LLDB.framework/lldb.so links against "liblldb-core.a" instead
of compiling the .o files only for the shared library. This fix
is only for compiling with Xcode as the Makefile based build already
does this.

The Xcode projecdt compiler has been changed to LLVM. Anyone using
Xcode 3 will need to manually change the compiler back to GCC 4.2,
or update to Xcode 4.

llvm-svn: 127963
2011-03-20 04:57:14 +00:00
Greg Clayton ded470d31a Added more platform support. There are now some new commands:
platform status -- gets status information for the selected platform
platform create <platform-name> -- creates a new instance of a remote platform
platform list -- list all available platforms
platform select -- select a platform instance as the current platform (not working yet)

When using "platform create" it will create a remote platform and make it the
selected platform. For instances for iPhone OS debugging on Mac OS X one can 
do:

(lldb) platform create remote-ios --sdk-version=4.0
Remote platform: iOS platform
SDK version: 4.0
SDK path: "/Developer/Platforms/iPhoneOS.platform/DeviceSupport/4.0"
Not connected to a remote device.
(lldb) file ~/Documents/a.out
Current executable set to '~/Documents/a.out' (armv6).
(lldb) image list
[  0] /Volumes/work/gclayton/Documents/devb/attach/a.out
[  1] /Developer/Platforms/iPhoneOS.platform/DeviceSupport/4.0/Symbols/usr/lib/dyld
[  2] /Developer/Platforms/iPhoneOS.platform/DeviceSupport/4.0/Symbols/usr/lib/libSystem.B.dylib


Note that this is all happening prior to running _or_ connecting to a remote
platform. Once connected to a remote platform the OS version might change which
means we will need to update our dependecies. Also once we run, we will need
to match up the actualy binaries with the actualy UUID's to files in the
SDK, or download and cache them locally.

This is just the start of the remote platforms, but this modification is the
first iteration in getting the platforms really doing something.

llvm-svn: 127934
2011-03-19 01:12:21 +00:00
Caroline Tice 77c13fe304 Fix various small problems with EmulateInstructionARM::EmulateSTRRtSP.
llvm-svn: 127898
2011-03-18 19:41:00 +00:00
Jim Ingham b7603bb48d Relax the constraint on the types of ValueObjects that we'll by default try the
ObjC runtime for print object to Pointer AND Integer (from just pointer.)

llvm-svn: 127841
2011-03-18 00:05:18 +00:00
Caroline Tice 4c753376cb Make all the codee that attempts to read the PC consistently use
ReadCoreReg (which 'does the right thing', adding to pc when needed);
fixed places in code where extra addition was being passed along.

Fix bug in insn tables.

llvm-svn: 127838
2011-03-17 23:50:16 +00:00
Jim Ingham 8268ccab60 Fix a problem where we were looking up the class pointer in the {class/sel -> implementation} cache for a objc_msgSendSuper call - where we should have looked up the class's super-class.
llvm-svn: 127830
2011-03-17 21:04:33 +00:00
Jim Ingham 35944dda10 Get ObjC stepping working again when the process is not the default host architecture.
llvm-svn: 127825
2011-03-17 20:02:56 +00:00
Caroline Tice aaf5ddcf82 Add code to emulate STRH (Register) Arm instruction.
Remove inaccurate comments from EmulateInstruction::Context definition.

Fix contexts in a few arm instruction emulation routines.

llvm-svn: 127770
2011-03-16 22:46:55 +00:00
Caroline Tice fe28f1bff9 Fix various small bugs found in the instruction emulation functions.
llvm-svn: 127712
2011-03-16 00:06:12 +00:00
Greg Clayton 3690964ca1 Added a fix that should help incorrect type uniquing. There was an issue
for templatized types that could cause parts of a std::vector (and I am sure
other STL types) to be incorrectly uniqued to each other wreaking havoc on 
variable display for types within the same executable module.

llvm-svn: 127662
2011-03-15 04:38:20 +00:00
Greg Clayton 616f490777 Added a fix to not re-use object files when doing DWARF with debug map.
llvm-svn: 127659
2011-03-15 03:56:33 +00:00
Sean Callanan fb0b7583a7 Updated to LLVM/Clang revision 127600.
llvm-svn: 127634
2011-03-15 00:17:19 +00:00
Stephen Wilson 1636265248 Add Makefile support for the Platform plugins.
This patch supports building the Linux platform plugin, and should also support
the MacOSX plugin as well (the MacOSX side has not been tested, unfortunately).
A small typo was corrected in lldb.cpp to initialize the new platform code on
Linux.

llvm-svn: 127393
2011-03-10 03:08:28 +00:00
Greg Clayton c574ede632 Centralize the GDB remote timeout value into the GDBRemoteCommunication as a
member variable (m_packet_timeout which is a value in seconds). This value is
then used for all packets sent to/from the remote GDB server.

llvm-svn: 127392
2011-03-10 02:26:48 +00:00
Sean Callanan b8205b1588 Fixed a bug where the disassembly syntax specified for the
ARM disassembler was wrong, causing the disassembler to fail
to initialize.

llvm-svn: 127302
2011-03-09 01:02:51 +00:00
Greg Clayton e996fd30be LLDB now has "Platform" plug-ins. Platform plug-ins are plug-ins that provide
an interface to a local or remote debugging platform. By default each host OS
that supports LLDB should be registering a "default" platform that will be
used unless a new platform is selected. Platforms are responsible for things
such as:
- getting process information by name or by processs ID
- finding platform files. This is useful for remote debugging where there is 
  an SDK with files that might already or need to be cached for debug access.
- getting a list of platform supported architectures in the exact order they
  should be selected. This helps the native x86 platform on MacOSX select the
  correct x86_64/i386 slice from universal binaries.
- Connect to remote platforms for remote debugging
- Resolving an executable including finding an executable inside platform
  specific bundles (macosx uses .app bundles that contain files) and also
  selecting the appropriate slice of universal files for a given platform.

So by default there is always a local platform, but remote platforms can be
connected to. I will soon be adding a new "platform" command that will support
the following commands:
(lldb) platform connect --name machine1 macosx connect://host:port
Connected to "machine1" platform.
(lldb) platform disconnect macosx

This allows LLDB to be well setup to do remote debugging and also once 
connected process listing and finding for things like:
(lldb) process attach --name x<TAB>

The currently selected platform plug-in can now auto complete any available
processes that start with "x". The responsibilities for the platform plug-in
will soon grow and expand.

llvm-svn: 127286
2011-03-08 22:40:15 +00:00
Stephen Wilson d126c8cc5a Fix ObjectFileElf::GetEntryPointAddress()
ELF object files do not implicitly have a symbol named "start" as an entry
point.  For example, on Linux it is often named "_start", but can be trivially
set to any symbol by passing an --entry argument to the linker.

Use the ELF header to determine the entry point and resolve the associated
section based on that address.

Also, update the linux dynamic loader to call GetEntryPointAddress instead of
GetEntryPoint.

llvm-svn: 127218
2011-03-08 04:12:15 +00:00
Stephen Wilson 8f0daa28d4 Add Makefile support for the new DynamicLoaderStatic plugin.
llvm-svn: 127215
2011-03-08 03:57:00 +00:00
Jim Ingham bd3f260698 I didn't notice there was already an ObjectFile::GetEntryPoint. Move that over to GetEntryPointAddress 'cause that's more consistent with other functions in ObjectFile, do the mutatis mutandi and also in the ELF case I return a section offset address rather than a bare load address.
llvm-svn: 127205
2011-03-08 01:54:01 +00:00
Jim Ingham 5ca40258ea Reverting the part of the debug-in-ofile patch from earlier today that removes them from the shared module list. That was causing a bunch of asserts. Greg is working on a better fix.
llvm-svn: 127201
2011-03-08 01:49:10 +00:00
Jim Ingham 672e6f59c5 Add a method "GetEntryPoint" to the ObjectFile class, and implement it on MachO & ELF - though the ELF implementation is probably a little weak. Then use this method in place of directly looking for "start" in the ThreadPlanCallFunction constructor to find the stopping point for our function evaluation.
llvm-svn: 127194
2011-03-07 23:44:08 +00:00
Greg Clayton 0bb165a7a7 Don't cache .o files in the debug map + DWARF in .o files. If we cache them
then we end up using older .o files with out of date section remappings if
we debug, compile + fix, and debug again.

llvm-svn: 127166
2011-03-07 18:51:54 +00:00
Greg Clayton fc7117ae93 Added a DynamicLoaderStatic plug-in that will act as a static dynamic loader.
It will just load all files exactly where the files state they are (file
addresses == load addresses). This is used when the llvm::Triple::OSType is
set to llvm::Triple::UnknownOS or llvm::Triple::NoOS.

llvm-svn: 127053
2011-03-05 01:04:56 +00:00
Greg Clayton 874472584d Allow the macosx frame backchain to use 32/64 bit as the selector when
chosing which FP back-chain methods to use since we can rely upon generic 
register numbers after that.

llvm-svn: 127044
2011-03-04 22:59:14 +00:00
Caroline Tice 94f87e37c8 Add code to emulate RFE Arm instruction.
Add new instruction context for RFE instruction.

Add several new helper functions to help emulate RFE instruction
(including CurrentModeIsPrivileged, BadMode, and CPSRWriteByInstr).

llvm-svn: 126965
2011-03-03 22:37:46 +00:00
Caroline Tice c8d0d3ae0b Add code to emulate UXTH Arm instruction.
llvm-svn: 126954
2011-03-03 18:48:58 +00:00
Caroline Tice 9c35f321c6 Add code to emulate UXTB Arm instruction.
llvm-svn: 126953
2011-03-03 18:27:17 +00:00
Caroline Tice 8678f2a192 Add code to emulate SXTH Arm instruction.
llvm-svn: 126951
2011-03-03 18:04:49 +00:00
Caroline Tice 67735bf069 Add code to emulate SXTB Arm instruction.
llvm-svn: 126949
2011-03-03 17:42:58 +00:00
Caroline Tice edc103e253 Fix bug where bitwise-AND was being used and it should have been bitwise-OR.
llvm-svn: 126904
2011-03-03 00:07:02 +00:00
Caroline Tice 30f40c6850 Add code to emulate ADD (immediate, Thumb) Arm instruction.
Add addition context to EmulateInstruction contexts.

llvm-svn: 126903
2011-03-02 23:57:02 +00:00
Caroline Tice 1a234ff46f Add code to emulate MUL Arm instruction.
Add new context type & info structure for  mul instruction.

llvm-svn: 126891
2011-03-02 22:43:54 +00:00
Greg Clayton 5f2a4f999d Added a missing API call in SBTarget that enables one to get
anything in a SBSymbolContext filled in given an SBAddress:

SBSymbolContext
SBTarget::ResolveSymbolContextForAddress (const SBAddress& addr, uint32_t resolve_scope);

Also did a little cleanup on the ProcessGDBRemote stdio file handle
code.

llvm-svn: 126885
2011-03-02 21:34:46 +00:00
Caroline Tice a0d3b67572 Add code to emulate LDRSH (register) Arm instruction.
llvm-svn: 126881
2011-03-02 21:13:44 +00:00
Caroline Tice 1cd4459b21 Add code to emulate LDRSH (literal) Arm instruction.
llvm-svn: 126866
2011-03-02 19:45:34 +00:00
Caroline Tice d3e57ee4fc Add code to emulate LDRSH (immediate) Arm instruction.
llvm-svn: 126807
2011-03-02 00:39:42 +00:00
Caroline Tice 4776fbbd72 Add code to emulate LDRSB (register) Arm instruction.
llvm-svn: 126802
2011-03-01 23:55:59 +00:00
Caroline Tice 4947ffc80d Add code to emulate LDRSB (literal) Arm instruction.
llvm-svn: 126789
2011-03-01 22:25:17 +00:00
Caroline Tice 28c3fcccb2 Add code to emulate LDRSB (immediate) Arm instruction.
llvm-svn: 126783
2011-03-01 21:53:03 +00:00
Caroline Tice 4f0e5f8852 Add code to emulate LDRH (register) Arm instruction.
llvm-svn: 126758
2011-03-01 18:00:42 +00:00
Caroline Tice 6261d240e1 Add code to emulate LDRH (literal) Arm instruction.
llvm-svn: 126709
2011-02-28 23:15:24 +00:00
Stephen Wilson bbb7e06ad3 Add register context for i386 on Linux.
Patch by Marco Minutoli!

llvm-svn: 126696
2011-02-28 22:52:38 +00:00
Caroline Tice adef8fb003 Add code to emulate LDRH (immediate, Thumb) arm instruction.
llvm-svn: 126692
2011-02-28 22:39:58 +00:00
Johnny Chen 699ac0e967 Add emulation for Encoding A1 of A8.6.97 MOV (register).
llvm-svn: 126456
2011-02-25 00:23:25 +00:00
Greg Clayton 7133762232 Fixed CommandReturnObject::SetImmediateErrorFile() to set the correct stream.
Modifed lldb_private::Process to be able to handle connecting to a remote 
target that isn't running a process. This leaves lldb_private::Process in the
eStateConnected state from which we can then do an attach or launch.

Modified ProcessGDBRemote to be able to set stdin, stdout, stderr, working
dir, disable ASLR and a few other settings down by using new GDB remote 
packets. This allows us to keep all of our current launch flags and settings
intact and still be able to communicate them over to the remote GDB server.
Previously these were being sent as arguments to the debugserver binary that
we were spawning. Also modified ProcessGDBRemote to handle losing connection
to the remote GDB server and always exit immediately. We do this by watching
the lldb_private::Communication event bit for the read thread exiting in the
ProcessGDBRemote async thread.

Added support for many of the new 'Q' packets for setting stdin, stdout,
stderr, working dir and disable ASLR to the GDBRemoteCommunication class for
easy accesss.

Modified debugserver for all of the new 'Q' packets and also made it so that
debugserver always exists if it loses connection with the remote debugger.

llvm-svn: 126444
2011-02-24 22:24:29 +00:00
Johnny Chen a517bae73c Fix typos in the opcode entries for branch instructions.
llvm-svn: 126442
2011-02-24 21:54:22 +00:00
Johnny Chen 3c970dc50d Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to
switch to Jazelle state fails, thus treating BXJ as a BX operation.

llvm-svn: 126423
2011-02-24 21:01:20 +00:00
Stephen Wilson 17e3d193e1 linux: Use ArchSpec::GetCore and the ArchSpec::Core enums.
llvm-svn: 126406
2011-02-24 19:17:09 +00:00
Stephen Wilson 3f4200fd9d linux: Remove a local ObjectFileELF version of GetArchitecture.
Also fix a bug where we were not lazily parsing the ELF header and thus
returning an ArchSpec with invalid cpu type components.  Initialize the cpu
subtype as LLDB_INVALID_CPUTYPE for compatibility with the new ArchSpec
implementation.

llvm-svn: 126405
2011-02-24 19:16:15 +00:00
Johnny Chen bf4afa8796 Add emulation methods for Bitwise Bit Clear (immediate and register) operations.
llvm-svn: 126355
2011-02-24 01:15:17 +00:00
Johnny Chen 132548df62 Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ARM)" operations.
llvm-svn: 126343
2011-02-23 23:47:56 +00:00
Johnny Chen d88d96cac9 Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience function
and rename the original ThumbImmScaled() function to ThumbImm7Scaled().

llvm-svn: 126335
2011-02-23 21:24:25 +00:00
Johnny Chen 5278cd11ba Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead of
Rd == 13.  Add opcode entries for the generic "sub (sp minus immediate)" operations.

llvm-svn: 126293
2011-02-23 01:55:07 +00:00
Johnny Chen 187b0e37c1 Add emulation methods for "SBC (immediate)" and "SBC (register)" operations.
llvm-svn: 126283
2011-02-23 01:01:21 +00:00
Greg Clayton 64195a2c8b Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified form
of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up
doing was:
- Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics
  the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple 
  to give us the machine type from llvm::Triple::ArchType.
- There is a new ArchSpec::Core definition which further qualifies the CPU
  core we are dealing with into a single enumeration. If you need support for
  a new Core and want to debug it in LLDB, it must be added to this list. In
  the future we can allow for dynamic core registration, but for now it is
  hard coded.
- The ArchSpec can now be initialized with a llvm::Triple or with a C string
  that represents the triple (it can just be an arch still like "i386").
- The ArchSpec can still initialize itself with a architecture type -- mach-o
  with cpu type and subtype, or ELF with e_machine + e_flags -- and this will
  then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core.
  The mach-o cpu type and subtype can be accessed using the getter functions:
  
  uint32_t
  ArchSpec::GetMachOCPUType () const;

  uint32_t
  ArchSpec::GetMachOCPUSubType () const;
  
  But these functions are just converting out internal llvm::Triple::ArchSpec 
  + ArchSpec::Core back into mach-o. Same goes for ELF.

All code has been updated to deal with the changes.

This should abstract us until later when the llvm::TargetSpec stuff gets
finalized and we can then adopt it.

llvm-svn: 126278
2011-02-23 00:35:02 +00:00
Johnny Chen 673badf292 Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs.
llvm-svn: 126271
2011-02-23 00:15:56 +00:00
Johnny Chen 7deb7422bc Add emulation methods for "RSC (immediate)" and "RSC (register)" operations.
llvm-svn: 126267
2011-02-23 00:07:09 +00:00
Johnny Chen 447c001048 Add emulation methods for "RSB (immediate)" and "RSB (register)".
Plus add missing break stmts for "case" blocks.

llvm-svn: 126265
2011-02-22 23:42:58 +00:00
Johnny Chen 5f88bcc16a Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() to ARMUtils.h.
Use them within EmulateInstructionARM.cpp to save repetitive typing.

llvm-svn: 126247
2011-02-22 21:17:52 +00:00
Johnny Chen 83a4ddd0cb Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method,
and implement EmulateCMNImm() and EMulateCMNReg() methods.

llvm-svn: 126236
2011-02-22 19:48:22 +00:00
Greg Clayton 681254c830 Remove an assertion that was causing a crash.
llvm-svn: 126235
2011-02-22 19:32:07 +00:00
Johnny Chen aebcfc86df Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should be ARMV6T2_ABOVE, not ARMvAll.
llvm-svn: 126234
2011-02-22 19:01:11 +00:00
Johnny Chen 01ceff367a Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations.
llvm-svn: 126179
2011-02-22 02:00:12 +00:00
Johnny Chen 5ea119468a Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations.
Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations,
with the EmulateCMNImm()/Reg() methods not implemented yet for now.

llvm-svn: 126178
2011-02-22 01:56:31 +00:00
Johnny Chen c2fa8fafde Add emulation methods for "MVN (immediate)" and "MVN (register)".
llvm-svn: 126172
2011-02-22 01:01:03 +00:00
Johnny Chen e69108a78f Add emulation methods for "EOR (Immediate)", "EOR (register)",
"TEQ (immediate)", and "TEQ (register)" operations.

llvm-svn: 126160
2011-02-21 23:42:44 +00:00
Johnny Chen 28c5882cb5 Add emulation methods for "TST (immediate)" and "TST (register)".
Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2
32-bit instructions when Rd == '1111' and setflags is true.

llvm-svn: 126144
2011-02-21 21:24:49 +00:00
Johnny Chen ce0dec7597 Make the helper method ReadCoreReg(uint32_t reg, bool *success) more generic
which now handles R0-R12, SP, LR, as well as PC.  And refactored a lot of
calls to ReadRegisterUnsigned() to now funnel through ReadCoreReg(), instead.

llvm-svn: 126010
2011-02-19 01:36:13 +00:00
Caroline Tice 55532be31f Add code to emulate LDRB (register) Arm instruction.
llvm-svn: 125994
2011-02-18 23:52:21 +00:00
Johnny Chen ce4e629fdf Add emulation methods for "ORR (immediate)" and "ORR (register)".
Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed
some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods.

llvm-svn: 125992
2011-02-18 23:41:11 +00:00
Caroline Tice 27d1032b60 Add code to emulate LDRB (literal) Arm instruction.
llvm-svn: 125975
2011-02-18 22:24:22 +00:00
Johnny Chen d1fd6963f5 Add emulation methods for "ADC (immediate)" and "ADC (register)".
Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify
coding a bit.

llvm-svn: 125961
2011-02-18 21:13:05 +00:00
Caroline Tice 489517c4a4 Add code to emulate LDRB (immediate, Thumb) instruction.
llvm-svn: 125959
2011-02-18 21:06:04 +00:00
Johnny Chen faba5dd4ae Add emulation methods for "AND (immediate)" and "AND (register)".
Plus add macro definitions for APSR_C and APSR_V to simplify code.

llvm-svn: 125947
2011-02-18 19:32:20 +00:00
Caroline Tice a1bf8db478 Add code to emulate LDR (register) Arm instruction.
llvm-svn: 125945
2011-02-18 18:52:37 +00:00
Johnny Chen f401d69c85 Fix typo.
llvm-svn: 125812
2011-02-18 01:26:39 +00:00
Johnny Chen fc9d00beb7 Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD (immediate, ARM)".
llvm-svn: 125809
2011-02-18 01:22:22 +00:00
Caroline Tice 29c9b64096 Add code to emulate LDR (immediate,ARM) instruction.
llvm-svn: 125808
2011-02-18 00:55:53 +00:00
Johnny Chen ae147cafa9 Finished renamings to make the emulation method names consistent case-wise.
llvm-svn: 125801
2011-02-18 00:07:39 +00:00
Johnny Chen a18ae1ffde Some renamings to make the emulation method names consistent case-wise.
llvm-svn: 125800
2011-02-18 00:02:28 +00:00
Johnny Chen d4926266f3 Removed redundant entry EmulateTBB() (there's an existing one EmulateTB()) and fixed some typos
in section headings.

llvm-svn: 125796
2011-02-17 23:44:53 +00:00
Johnny Chen 2a7e05a3d7 Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice"
the value of the byte/halfword returned from the table.

llvm-svn: 125793
2011-02-17 23:27:44 +00:00
Caroline Tice 16443905f3 Add header declarations for the remaining instructions we need to
emulate, to cover those that can change the PC.

llvm-svn: 125791
2011-02-17 23:09:13 +00:00
Johnny Chen 34dd9ba9c7 Refactoring. Abstracted the set flags operation into its own helper method
WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags().
Modified the call sites to use the helper methods.

llvm-svn: 125788
2011-02-17 22:37:12 +00:00
Johnny Chen fc5c19dec5 A8.6.6 ADD (register)
Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it.
Where Encoding T2 can potentially modify the PC, causing a brnach.

llvm-svn: 125782
2011-02-17 22:03:29 +00:00
Johnny Chen 2789706059 Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch Halfword"
operations for Thumb2.

llvm-svn: 125767
2011-02-17 19:34:27 +00:00
Caroline Tice 032d2dd576 Add stubs for pseudocode functions "MemA[]" amd "MemU[]", corresponding to aligned
and unaligned memory accesses.  The new stub functions are MemARead, MemAWrite,
MemURead, and MemUWrite.  At the moment these stubs just call ReadMemoryUnsigned or
WriteMemoryUnsigned, but we can fill them out further later if we decide we need
more accurate emulation of the memory system.

Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in
EmulateInstructionARM.cpp with calls to the appropriate new stub function.

llvm-svn: 125766
2011-02-17 19:20:40 +00:00
Johnny Chen 0f60574fd7 Move Align(val, alignment) utility function to ARMUtils.h.
llvm-svn: 125753
2011-02-17 17:31:08 +00:00
Johnny Chen e19e4fc8dc Add comment for the helper method WriteCoreRegisterWithFlags().
llvm-svn: 125703
2011-02-17 01:49:00 +00:00
Johnny Chen 0c64b5bbb6 Refactoring. Wrap the following pseudocode from the ARM Architecture Reference Manul:
// if d == 15 then         // Can only occur for encoding A1
//     ALUWritePC(result); // setflags is always FALSE here
// else
//     R[d] = result;
//     if setflags then
//         APSR.N = result<31>;
//         APSR.Z = IsZeroBit(result);
//         APSR.C = carry;
//         // APSR.V unchanged

into a helper method WriteCoreRegisterWithFlags, and modified the existing methods
to take advantage of it.

Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register).

llvm-svn: 125701
2011-02-17 01:35:27 +00:00
Greg Clayton f4ecaa576c Clean up a bit of the type getting code where lldb_private:Type now has
clang_type_t
    GetClangFullType(); // Get a completely defined clang type

    clang_type_t
    GetClangLayoutType(); // Get a clang type that can be used for type layout
    
    clang_type_t
    GetClangForwardType(); // A type that can be completed if needed, but is more efficient.
    

llvm-svn: 125691
2011-02-16 23:00:21 +00:00
Johnny Chen 4890c85e0a Add emulation methods for ROR (immediate), ROR (register), and RRX.
Turns out that they can be funneled through the helper methods
EmulateShiftImm()/ EmulateShiftReg() as well.

Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX.
And fix a typo in the impl of utility Shift_C() in ARMUtils.h.

llvm-svn: 125689
2011-02-16 22:14:44 +00:00
Caroline Tice eaf2e4fdf1 Add code to emulate STRB (Thumb) instruction.
llvm-svn: 125686
2011-02-16 20:22:22 +00:00
Johnny Chen 14571f4b67 Add encoding entries for LSL (immediate and register) and LSR (immediate and register) to
ARM and Thumb opcode tables.

llvm-svn: 125683
2011-02-16 19:27:43 +00:00
Johnny Chen 4b22e7e67a Add tagging for EmulateLDRRtRnImm().
llvm-svn: 125671
2011-02-16 18:35:47 +00:00
Stephen Wilson 7a86fcdd8f Make declaration of DynamicLoaderLinuxDYLD::CreateInstance match its definition.
llvm-svn: 125656
2011-02-16 05:38:31 +00:00
Stephen Wilson de049291fd linux: Set ArchSpec m_type correctly from object file.
An ArchSpec's type defaults to MachO.  Ensure the type is properly set
on ELF systems.

llvm-svn: 125654
2011-02-16 05:25:13 +00:00
Greg Clayton 93d3c8339c The DynamicLoader plug-in instance now lives up in lldb_private::Process where
it should live and the lldb_private::Process takes care of managing the 
auto pointer to the dynamic loader instance.

Also, now that the ArchSpec contains the target triple, we are able to 
correctly set the Target architecture in DidLaunch/DidAttach in the subclasses,
and then the lldb_private::Process will find the dynamic loader plug-in 
by letting the dynamic loader plug-ins inspect the arch/triple in the target.

So now the ProcessGDBRemote plug-in is another step closer to be purely 
process/platform agnostic.

I updated the ProcessMacOSX and the ProcessLinux plug-ins accordingly.

llvm-svn: 125650
2011-02-16 04:46:07 +00:00
Johnny Chen 0f03baa539 Minor comment change.
llvm-svn: 125634
2011-02-16 01:31:20 +00:00
Johnny Chen 22deaa5a1a Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register).
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR
delegate to the helper methods which take an extra ARM_ShifterType parameter.

The opcodes tables have not been updated yet to reflect these new entries.

llvm-svn: 125633
2011-02-16 01:27:54 +00:00
Caroline Tice 5b5396ba77 Add documentation tags for LDM/STM instruction families.
Add code to emulate STR (register) Arm instruction.

llvm-svn: 125623
2011-02-16 00:33:43 +00:00
Johnny Chen a79703db79 Section heading for EmulateB().
llvm-svn: 125620
2011-02-16 00:17:18 +00:00
Johnny Chen 7484e4e337 Add section headings corresponding to some of the ARM/Thumb emulation methods for better documentation.
llvm-svn: 125618
2011-02-16 00:06:18 +00:00
Greg Clayton bdda58377f Fixed an issue where detection of vCont support wasn't being done correctly.
Fixed how the LLDBDisassembler computes and uses a target triple.

llvm-svn: 125617
2011-02-16 00:00:43 +00:00
Johnny Chen 531dbfa5d8 A8.6.14 ASR (register)
Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125614
2011-02-15 23:22:46 +00:00
Caroline Tice f199eea579 Add eContextRegisterLoad instruction emulation context.
Add code to emulate STR (Immediate, Thumb) instruction.

llvm-svn: 125610
2011-02-15 22:53:54 +00:00
Johnny Chen f35024b087 Modify the various shift routines to handle cases where the shift amount comes
from the bottom byte of a register.

llvm-svn: 125606
2011-02-15 22:21:33 +00:00
Greg Clayton 514487e806 Made lldb_private::ArchSpec contain much more than just an architecture. It
now, in addition to cpu type/subtype and architecture flavor, contains:
- byte order (big endian, little endian)
- address size in bytes
- llvm::Triple for true target triple support and for more powerful plug-in
  selection.

llvm-svn: 125602
2011-02-15 21:59:32 +00:00
Johnny Chen f976896b83 Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC()
methods of EmulateInstructionARM class.  The context data structure should provide sufficient
information already.

llvm-svn: 125596
2011-02-15 21:08:58 +00:00
Johnny Chen 6f93f63955 Fix wrong mask and encoding for T2 of ASR (immediate).
llvm-svn: 125593
2011-02-15 20:14:02 +00:00
Johnny Chen a4afff97ad A8.6.14 ASR (immediate)
Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125592
2011-02-15 20:10:55 +00:00
Caroline Tice 6e12e117d4 Add code to emulate STMIB Arm instruction.
llvm-svn: 125580
2011-02-15 18:42:15 +00:00
Caroline Tice 5e38f35fe3 Add code to emulate STMDB Arm instruction.
Add some bit-mask fixes to code for getting register bits for various LDM and STM instructions.

llvm-svn: 125578
2011-02-15 18:10:01 +00:00
Johnny Chen 7a03c852d0 Add a bunch of utilities and an enum (ARM_ShifterType) for shift and rotate operations pertaining to:
o A2.2.1 Pseudocode details of shift and rotate operations
o A8.4.3 Pseudocode details of instruction-specified shifts and rotates

llvm-svn: 125575
2011-02-15 17:52:22 +00:00
Johnny Chen ef55e4c174 Remove the unnecessary assignment of m_inst_cpsr inside EvaluateInstruction(),
because it's already been done within ReadInstruction().

llvm-svn: 125569
2011-02-15 17:31:33 +00:00
Caroline Tice efb309619a Add code to emulate the STMDA Arm instruction.
llvm-svn: 125542
2011-02-15 00:19:42 +00:00
Greg Clayton e576ab2996 All UnwindPlan objects are now passed around as shared pointers.
ArchDefaultUnwindPlan plug-in interfaces are now cached per architecture 
instead of being leaked for every frame.

Split the ArchDefaultUnwindPlan_x86 into ArchDefaultUnwindPlan_x86_64 and
ArchDefaultUnwindPlan_i386 interfaces.

There were sporadic crashes that were due to something leaking or being 
destroyed when doing stack crawls. This patch should clear up these issues.

llvm-svn: 125541
2011-02-15 00:19:15 +00:00
Johnny Chen 557520b996 Add missing logic (if BadReg(d) then UNPREDICTABLE;) for Encoding T2 of EmulateMovRdImm().
llvm-svn: 125533
2011-02-14 23:33:58 +00:00
Johnny Chen 5623dc3559 Fix build warning (unused variable).
llvm-svn: 125531
2011-02-14 23:21:24 +00:00
Caroline Tice eccad4d005 - Rearrange instruction emulation contexts to use a union for the
various types and numbers of arguments rather than trying to keep a
  constant number of arguments for all the types.

- Also create a Register type within the instructions, to hold
  register type and number.

- Modify EmulateInstructionArm.cpp to use the new register and context
  types in all the instruction emulation functions.

- Add code to emulate the STM Arm instruction.

llvm-svn: 125528
2011-02-14 23:03:21 +00:00
Johnny Chen c3ba12d8e8 Add entries for EmulateMovRdImm() -- "MOV (immediate)" -- Encodings T1 & T2 into g_thumb_opcodes
table.  Modify EmulateInstructionARM::EvaluateInstruction() so that if the cpsr has changed
during evaluate instruction, we flush out the change into m_inst_cpsr in preparation for the next
instruction.

llvm-svn: 125524
2011-02-14 22:04:25 +00:00
Johnny Chen 86776147ff Add impl for EmulateMvnRdImm() -- "MVN (immediate)". Plus zero out the arg0 field of
the context of eContextImmediate type, since the immediate value is known from the
argument value to WriteRegisterUnsigned() callback already.

llvm-svn: 125518
2011-02-14 20:39:01 +00:00
Johnny Chen ac407594c2 Add comment.
llvm-svn: 125509
2011-02-14 19:09:36 +00:00
Johnny Chen e2b86a3a83 Enhanced the existing ARMExpandImm() and ThumbExpandImm() functions which expand
an imm12 into imm32 for ARM or Thumb so that they now handle carry_in/carry_out.
Funnel ARMExpandImm()/ThumbExpandImm() to the enhanced ARMExpandImm_C()/ThumbExpandImm_C()
functions.

llvm-svn: 125508
2011-02-14 19:08:41 +00:00
Greg Clayton 71fc2a33b5 Added the ability to detect which vCont packets (using the "vCont?") packet
are supported by the remote GDB target. We can also now deal with the lack of
vCont support and send packets that the remote GDB stub can use. We also error
out of the continue if LLDB tries to do something too complex when vCont isn't
supported.

llvm-svn: 125433
2011-02-12 06:28:37 +00:00
Johnny Chen b3b8e0ffc2 Add entries for Encodings T1 and A1 of "MVN (immediate)" to g_arm_opcodes and g_thumb_opcodes
tables.  The corresponding EmulateMvnRdImm() method impl is empty for now.

llvm-svn: 125425
2011-02-12 01:27:26 +00:00
Johnny Chen 61938f795f Changed comments of some functions to be consistent with existing ones.
llvm-svn: 125423
2011-02-12 01:01:40 +00:00
Johnny Chen 1173fbdc4b Add helper methods InITBlock() and LastInITBlock() to EmulateInstructionARM class
instead of calling out to m_it_session.InITBlock()/LastInITBlock(), which simplifies
the coding a bit.

llvm-svn: 125421
2011-02-12 00:50:05 +00:00
Johnny Chen a222c04588 Add EmulateBXRm() ("Branch and Exchange") to both g_arm_opcodes and g_thumb_opcodes table.
llvm-svn: 125418
2011-02-12 00:10:51 +00:00
Johnny Chen 722d4e4aa0 Add a couple of utility functions plus some comments.
llvm-svn: 125416
2011-02-11 23:29:14 +00:00
Caroline Tice 7b37670d56 - Add three more instruction contexts to EmulateInstruction:
eContextAdjustBaseRegister, eContextRegisterStore and
eContextWriteMemoryRandomBits.

- Implement a version of WriteBits32UnknownToMemory for writing to memory.

- Modify EmulateLDM, EmulateLDMDA, EmulateLDMDB and EmulateLDMIB to use the
eContextAdjustBaseRegister context when appropriate.

- Add code to emulate the STM/STMIA/STMEA Arm instruction.

llvm-svn: 125414
2011-02-11 22:49:54 +00:00
Johnny Chen a61541663c Add EmulateCmpRnRm() for Encodings T1 & T2 to the g_thumb_opcodes table to emulate
CMP (register) operations.

llvm-svn: 125413
2011-02-11 21:53:58 +00:00
Johnny Chen c6ca7bb67a Rearraned some emulate instruction entries under the appropriate category.
llvm-svn: 125405
2011-02-11 21:23:32 +00:00
Johnny Chen f1075ce0e6 Handle the case of interworking branch for EmulateLDMDA.
llvm-svn: 125392
2011-02-11 19:37:03 +00:00
Johnny Chen 298251cd9b Add Thumb2 LDR (literal) instruction into the g_thumb_opcodes table.
Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant
with the ARM Arch Manual which uses Rt for the destination register.

llvm-svn: 125390
2011-02-11 19:12:30 +00:00
Johnny Chen bce7ad6b48 Fix build.
llvm-svn: 125379
2011-02-11 18:11:22 +00:00
Caroline Tice 485b4d8352 Add new instruction context, eContextWriteRegisterRandomBits.
Add new utility function, WriteBits32Unknown

Modify the LDM* instruction emulation functions to call WriteBits32Unknown.
Add missing overview comments to the LDM* instruction emulation functions.

Add code to emulate LDMDA Arm instruction.

llvm-svn: 125377
2011-02-11 17:59:55 +00:00
Johnny Chen c7af6fe3bd Add an entry for CMP (immediate) (Encoding T1) to the g_thumb_opcodes table.
llvm-svn: 125333
2011-02-11 02:02:56 +00:00
Johnny Chen 37c48b02a4 Add a helper method AddWithCarry() to the EmulateInstructionARM class.
llvm-svn: 125329
2011-02-11 01:29:53 +00:00
Johnny Chen 9524110d98 Cleaned up some parameter types and names.
llvm-svn: 125313
2011-02-10 21:49:16 +00:00
Johnny Chen c843a78efc Namings are important. Renamed Bits32(const uint32_t val, uint32_t bit) to Bit32(val, bit) and
SetBits32(uint32_t &bits, uint32_t bit, uint32_t val) to SetBit32(bits, bit, val).

llvm-svn: 125312
2011-02-10 21:39:01 +00:00
Johnny Chen 101f6efb8a Some refactorings to use the convenience function: Bits32(const uint32_t value, const uint32_t bit).
llvm-svn: 125303
2011-02-10 19:54:05 +00:00
Johnny Chen 992b48c4be Add some comment markers.
llvm-svn: 125302
2011-02-10 19:40:42 +00:00
Johnny Chen 0cfda5bbb5 Add a generic EmulateMovRdRm() method and modify/add entries to the g_thumb_opcodes
table.  Also add some more defines and convenience functions.

llvm-svn: 125300
2011-02-10 19:29:03 +00:00
Johnny Chen 77224a5422 Rearrange the order of g_thumb_opcodes entries.
llvm-svn: 125295
2011-02-10 18:13:23 +00:00
Johnny Chen cc13e4c62e Add EmulateLDRRtRnImm() for EncodingT1 of LDR (immediate, Thumb) to the g_thumb_opcodes table,
and a helper method UnalignedSupport().

llvm-svn: 125258
2011-02-10 01:52:38 +00:00
Johnny Chen 1cabebe7bc Add a new member variable m_new_inst_cpsr to catch the to-be-updated state
of the CPSR during the course of executing an opcode, and modified SelectInstrSet()
to update this variable instead of the original m_inst_cpsr, which should be
the cached copy of the CPSR at the beginning of executing the opcode.

llvm-svn: 125244
2011-02-09 23:59:17 +00:00
Johnny Chen edf55ae52a Add EmulateAddRdnRm() for EncodingT2 of ADD(register) to the g_thumb_opcodes table,
and a helper method ALUWritePC(Context&, uint32_t).

llvm-svn: 125241
2011-02-09 23:43:29 +00:00
Greg Clayton 7bd65b9fae Modified version of a patch from Warren Paul that takes care of issues with
indirect forms, deals with empty DW_AT_comp_dir attributes, and fixups for
handling other signed integer types.

llvm-svn: 125240
2011-02-09 23:39:34 +00:00
Johnny Chen 0ce4a83c44 Modified existing Emulate* methods to call LoadWritePC(context, data) where appropriate to
effect an interworking branch if the ArchVersion() is ARMv5T and above.

llvm-svn: 125227
2011-02-09 22:02:17 +00:00
Stephen Wilson d4182f4b01 linux: use IS_VALID_LLDB_HOST_THREAD.
Update the linux plugin code to use the new check for a valid host
thread introduced in r125067.

llvm-svn: 125213
2011-02-09 20:10:35 +00:00
Johnny Chen 8bba644bf4 Modified EmulatePop impl to use the helper method LoadWritePC(context, data) since if PC
is in the list of registers to be load and we're in ARMv5T and above, this is an interworking branch.

llvm-svn: 125212
2011-02-09 19:30:49 +00:00
Johnny Chen cc707657f9 If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
we want to record it and issue a WriteRegister callback so the clients
can track the mode changes accordingly.

llvm-svn: 125209
2011-02-09 19:11:32 +00:00