3f1a92468a
Use ldr.n to workaround a darwin assembler bug.
...
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
76a4774a0d
Move subtarget check upper for NEON reg-reg fixup pass.
...
llvm-svn: 85914
2009-11-03 18:46:11 +00:00
31c2f4701b
Trim unnecessary include.
...
llvm-svn: 85878
2009-11-03 07:08:08 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
...
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
23c009f125
Clean up copyRegToReg.
...
llvm-svn: 85870
2009-11-03 05:51:39 +00:00
9e9079371c
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
...
llvm-svn: 85869
2009-11-03 05:50:57 +00:00
187cb4f493
Update CMake file.
...
llvm-svn: 85861
2009-11-03 04:14:12 +00:00
d195f9e5c3
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
...
llvm-svn: 85850
2009-11-03 01:04:26 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
b389f2a04d
Revert previous change to a comment. The BlockAddresses go in the
...
constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
d9dfc2e752
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
...
have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
4c00a524eb
Hyphenate some comments.
...
llvm-svn: 85808
2009-11-02 17:10:37 +00:00
433ab09ca3
Add support for BlockAddress values in ARM constant pools.
...
llvm-svn: 85806
2009-11-02 16:59:06 +00:00
e90a4aa703
Prune unnecessary include.
...
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
115cfc07d5
These are done / no longer care.
...
llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
...
llvm-svn: 85797
2009-11-02 07:51:19 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
...
llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1a4492be97
Fix a couple more places where we are creating ld / st instructions without memoperands.
...
llvm-svn: 85746
2009-11-01 22:04:35 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
...
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
...
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
...
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
8be42bd09f
Updates to the ARM target assembler for llvm-mc per review comments from
...
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
llvm-svn: 85632
2009-10-30 22:55:57 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
...
llvm-svn: 85624
2009-10-30 22:22:46 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
...
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
6b00f4b7a8
Fix a comment.
...
llvm-svn: 85610
2009-10-30 20:13:25 +00:00
ab7c709f43
This fixes functions like
...
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
f7c4299312
Initial x86 support for BlockAddresses.
...
llvm-svn: 85557
2009-10-30 01:28:02 +00:00
8578068302
Dial back the realignment a bit.
...
llvm-svn: 85546
2009-10-30 00:08:40 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
...
realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
...
I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
...
llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
...
llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
...
llvm-svn: 85381
2009-10-28 06:55:03 +00:00
f64db3e1d0
X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes.
...
llvm-svn: 85379
2009-10-28 06:30:34 +00:00
a91a563530
Previously, all operands to Constant were themselves constant.
...
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.
llvm-svn: 85375
2009-10-28 05:14:34 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
...
llvm-svn: 85362
2009-10-28 01:44:26 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
...
llvm-svn: 85361
2009-10-28 01:43:28 +00:00
9c6bc1f563
Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
...
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
llvm-svn: 85357
2009-10-28 00:55:57 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
...
llvm-svn: 85355
2009-10-28 00:37:03 +00:00
d04cb6d0fa
rename indbr -> indirectbr to appease the residents of #llvm.
...
llvm-svn: 85351
2009-10-28 00:19:10 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
...
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
2e5198ff09
Add new note.
...
llvm-svn: 85341
2009-10-27 23:30:07 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
...
llvm-svn: 85335
2009-10-27 22:52:29 +00:00
fd2730ee8c
Move and clarify note.
...
llvm-svn: 85334
2009-10-27 22:48:31 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
...
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
2974f63cb5
Note corrected.
...
llvm-svn: 85332
2009-10-27 22:43:24 +00:00
cd4d148040
Modify note.
...
llvm-svn: 85331
2009-10-27 22:40:45 +00:00
a205402c16
Add a note.
...
llvm-svn: 85329
2009-10-27 22:34:43 +00:00
e8628a0206
cppbackend support for indbr
...
llvm-svn: 85312
2009-10-27 21:24:48 +00:00
42c979e8d3
CBE support for indbr.
...
llvm-svn: 85311
2009-10-27 21:21:06 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
...
llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
...
BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
...
llvm-svn: 85281
2009-10-27 19:56:55 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
...
instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
...
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
a789f17ffc
Remove unnecessary gotos to fall-thru successors.
...
llvm-svn: 85257
2009-10-27 17:40:24 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
...
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
fb22a85baf
apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :(
...
llvm-svn: 85252
2009-10-27 17:01:03 +00:00
d90d169f9d
Correctly align double arguments in the stack.
...
llvm-svn: 85235
2009-10-27 14:09:44 +00:00
538984c1c3
Now VFP instructions.
...
llvm-svn: 85186
2009-10-27 00:20:49 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85178
2009-10-26 23:45:59 +00:00
de5ad42aa1
Remove FreeInst.
...
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.
llvm-svn: 85176
2009-10-26 23:43:48 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
...
bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
...
Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
...
bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
ce8f626f82
Update CMake files.
...
llvm-svn: 85161
2009-10-26 22:06:01 +00:00
0ae1b2961d
Revert r85134, it breaks mingw build
...
llvm-svn: 85138
2009-10-26 18:40:24 +00:00
752aea6513
Make PIC16 overlay a loadable pass.
...
llvm-svn: 85134
2009-10-26 18:22:59 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
56869f22c4
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
...
direct inclusion edge from System to Support.
llvm-svn: 85086
2009-10-26 01:35:46 +00:00
5bde1cbd93
of -> or
...
llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
...
llvm-svn: 85064
2009-10-25 18:55:46 +00:00
b18a46806b
Reapply 85006 with a minor fix.
...
llvm-svn: 85052
2009-10-25 08:14:11 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
...
llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
...
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
13b8b56dd4
this is done.
...
llvm-svn: 85041
2009-10-25 06:17:51 +00:00
54d7179a25
Remove ICmpInst::isSignedPredicate which was a reimplementation
...
CmpInst::isSigned.
llvm-svn: 85037
2009-10-25 05:20:17 +00:00
9e8d42f295
Revert back 85006 for now as it breaks PIC16 tests.
...
llvm-svn: 85008
2009-10-24 18:19:41 +00:00
055c3305a1
Adding support for placing global objects in shared data memory.
...
llvm-svn: 85006
2009-10-24 18:02:44 +00:00
46ed1f8341
80 col violation.
...
llvm-svn: 84986
2009-10-24 02:07:42 +00:00
e2871d69db
Restrict Thumb1 register allocation to low registers, even for instructions that
...
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
llvm-svn: 84982
2009-10-24 00:19:24 +00:00
22b2c011f9
FIXME no longer applies. R12 and R3 are available for allocation
...
llvm-svn: 84977
2009-10-23 23:07:42 +00:00
851193b873
some stuff is done, we still have constantexpr simplification to do.
...
llvm-svn: 84943
2009-10-23 07:00:55 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
...
llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
c77f8634e5
Shift art to the right to keep GCC from complaining about multi-line comments.
...
llvm-svn: 84849
2009-10-22 09:28:49 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
943f4f41f2
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
...
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
5457a96b63
Trim more includes.
...
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
344fcd9d61
Trim include.
...
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
1448799377
fix warning.
...
llvm-svn: 84826
2009-10-22 03:42:27 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f1ad2c618a
Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
...
Yay for ASCII graphics!
llvm-svn: 84808
2009-10-22 00:16:00 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
...
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
b45d621ab1
Revert r84764, it breaks mingw build
...
llvm-svn: 84783
2009-10-21 21:15:18 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
9e92857b38
Add DAG printing for RMW stuff debugging
...
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
...
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
5399c2d05e
Implement branch folding
...
llvm-svn: 84774
2009-10-21 19:17:18 +00:00
2983dcb1f2
Cosmetic changes, no functionality changes
...
llvm-svn: 84773
2009-10-21 19:16:49 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
c5804f3cb6
Build shared lib instead of an archive.
...
llvm-svn: 84764
2009-10-21 17:27:23 +00:00
47ea743618
Add a pass to overlay pic16 data sections for function frame and automatic
...
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.
llvm-svn: 84753
2009-10-21 10:42:44 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
175d04c90f
tidy
...
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
bc69313909
IPSCCP is missing stuff.
...
llvm-svn: 84725
2009-10-21 01:10:37 +00:00
7099d0c19c
Add note
...
llvm-svn: 84713
2009-10-21 00:14:15 +00:00
e43af4a085
Be crazy and assert in case of unsupported modifier passed.
...
llvm-svn: 84712
2009-10-21 00:13:58 +00:00
11074fa73e
Handle external symbols
...
llvm-svn: 84711
2009-10-21 00:13:42 +00:00
cc55b9086d
Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting.
...
llvm-svn: 84710
2009-10-21 00:13:25 +00:00
94ba9c27b0
Add basic block operands & jump kinds
...
llvm-svn: 84709
2009-10-21 00:13:05 +00:00
8a06a4e5c8
Ignore all implicit reg operands
...
llvm-svn: 84708
2009-10-21 00:12:44 +00:00
196b0e5431
Add a workaround for different memops prefixes
...
llvm-svn: 84707
2009-10-21 00:12:27 +00:00
4e32bff382
Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries
...
llvm-svn: 84706
2009-10-21 00:12:08 +00:00
7fbc0a50d5
Add simple operand printing stuff
...
llvm-svn: 84704
2009-10-21 00:11:27 +00:00
6e78029d82
Add experimental MSP430 MCInstLowering stuff
...
llvm-svn: 84703
2009-10-21 00:11:08 +00:00
daaa2f0c31
Wire up MSP430 printMCInst() method
...
llvm-svn: 84702
2009-10-21 00:10:47 +00:00
b6e2e4fd50
Add MSP430 InstPrinter stub
...
llvm-svn: 84701
2009-10-21 00:10:30 +00:00
13de81ac40
Use proper target data
...
llvm-svn: 84700
2009-10-21 00:10:00 +00:00
a470eac6a1
Fix -Asserts warning.
...
llvm-svn: 84687
2009-10-20 22:10:05 +00:00
cccf5084a3
Disable by default while debugging
...
llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
...
llvm-svn: 84664
2009-10-20 20:19:50 +00:00
3d9d78463c
Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.
...
llvm-svn: 84652
2009-10-20 18:14:49 +00:00
4a43e3068d
Make TranslateX86CC return COND_INVALID instead of aborting when it
...
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
llvm-svn: 84640
2009-10-20 16:22:37 +00:00
3301207a15
Random #include pruning.
...
llvm-svn: 84632
2009-10-20 11:44:38 +00:00
8296e62244
This file is replaeced by PIC16Section.h.
...
llvm-svn: 84628
2009-10-20 09:16:32 +00:00
9351e4f4b2
implement some more easy hooks.
...
llvm-svn: 84614
2009-10-20 06:22:33 +00:00
60d5131653
Implement some hooks, make printOperand abort if unknown modifiers are
...
present.
llvm-svn: 84613
2009-10-20 06:15:28 +00:00
227767b4e5
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
...
llvm-svn: 84611
2009-10-20 05:58:02 +00:00
f0b3d15cfe
Wire up the ARM MCInst printer, for llvm-mc.
...
llvm-svn: 84600
2009-10-20 05:15:36 +00:00
34f040a575
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
...
functions are not needed.
llvm-svn: 84587
2009-10-20 01:32:47 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
...
llvm-svn: 84585
2009-10-20 01:26:58 +00:00
484d2e9491
lower ARM::MOVi32imm properly.
...
llvm-svn: 84583
2009-10-20 01:11:37 +00:00
43c5589a7e
add support for external symbols. The mc instprinter can now handle
...
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
llvm-svn: 84582
2009-10-20 00:56:16 +00:00
1b06acbd70
get fancy: support basic block operands. Yay for jumps.
...
llvm-svn: 84579
2009-10-20 00:52:47 +00:00
85ab670644
add supprort for the 'sbit' operand, MOVi apparently has one.
...
llvm-svn: 84577
2009-10-20 00:46:11 +00:00
19c52201bd
add support for instruction predicates.
...
llvm-svn: 84575
2009-10-20 00:42:49 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
...
llvm-svn: 84573
2009-10-20 00:40:56 +00:00
772b2f84eb
Refs: A8-598.
...
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
68f495caad
Add missing encoding bits to NLdSt class of instructions.
...
Patch by Johnny Chen.
llvm-svn: 84570
2009-10-20 00:19:08 +00:00
0b4a59fc07
X86 should ignore implicit regs when lowering to MCInst also,
...
no functionality change.
llvm-svn: 84567
2009-10-19 23:35:57 +00:00
bd531262f8
handle addmode4 modifiers, fix a fixme in printRegisterList
...
by ignoring all implicit regs when lowering.
llvm-svn: 84566
2009-10-19 23:31:43 +00:00
d99b6974b9
simplify by using the twine form of GetOrCreateSymbol
...
llvm-svn: 84565
2009-10-19 23:05:23 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
...
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
d91c11091d
use EmitLabel instead of text emission
...
llvm-svn: 84562
2009-10-19 22:51:16 +00:00
86dfd73c38
add a twine version of MCContext::GetOrCreateSymbol.
...
llvm-svn: 84561
2009-10-19 22:49:00 +00:00
186c6b0834
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
...
like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
llvm-svn: 84558
2009-10-19 22:33:05 +00:00
5a5a3bc5d4
Adjust the scavenge register spilling to allow the target to choose an
...
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
llvm-svn: 84554
2009-10-19 22:27:30 +00:00
add5749ac8
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
...
llvm-svn: 84553
2009-10-19 22:23:04 +00:00
ef2979b1da
add register list and hacked up addrmode #4 support, we now get this:
...
_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
llvm-svn: 84546
2009-10-19 22:09:23 +00:00
f264f8a21c
revert r84540, fixing build breakage I didn't see because of
...
broken makefile deps :(
llvm-svn: 84544
2009-10-19 21:59:25 +00:00
7ddfdc4133
add addrmode2 support, getting us up to:
...
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
llvm-svn: 84543
2009-10-19 21:57:05 +00:00
889a6217fa
add jump tables, constant pools and some trivial global
...
lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
llvm-svn: 84542
2009-10-19 21:53:00 +00:00
e3796a0fee
pass mangler in as a reference instead of a pointer.
...
llvm-svn: 84540
2009-10-19 21:45:31 +00:00
8bd9b9d3fa
reduce #includes
...
llvm-svn: 84536
2009-10-19 21:23:15 +00:00
89d47205b5
add printing support for SOImm operands, getting us to:
...
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
llvm-svn: 84535
2009-10-19 21:21:39 +00:00
93e3ef6536
wire up some basic printOperand goodness, giving us stuff like this before
...
we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
llvm-svn: 84532
2009-10-19 20:59:55 +00:00
78393d79a0
add the files that go with the previous rev
...
llvm-svn: 84531
2009-10-19 20:21:05 +00:00
71eb077c15
wire up skeletal support for having llc print instructions
...
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
llvm-svn: 84530
2009-10-19 20:20:46 +00:00
296544e15f
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
...
"something" when printing MCInsts, it will just be missing all the
operand info.
llvm-svn: 84528
2009-10-19 19:59:05 +00:00
a290778859
stub out a minimal ARMInstPrinter.
...
llvm-svn: 84527
2009-10-19 19:56:26 +00:00
5db7b6a5d4
remove strings from instructions who are never asmprinted.
...
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase. If they got to
the asmprinter, they would explode. They should eventually
be replace with correct use of subregs.
llvm-svn: 84526
2009-10-19 19:51:42 +00:00
8d2e3a28d6
simplify code, reducing string thrashing.
...
llvm-svn: 84521
2009-10-19 18:49:14 +00:00
3334deb19b
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
...
llvm-svn: 84520
2009-10-19 18:44:38 +00:00
6462adcd20
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
...
llvm-svn: 84519
2009-10-19 18:38:33 +00:00
24fcb826bd
remove dead map
...
llvm-svn: 84513
2009-10-19 18:11:25 +00:00
84a493ca21
don't bother trying to avoid emitting redundant constant pool alignment directives.
...
llvm-svn: 84512
2009-10-19 18:08:02 +00:00
66ebfab3ab
remove accidental comment.
...
llvm-svn: 84510
2009-10-19 18:03:41 +00:00
e6da1826e8
emit .subsections_via_symbols through MCStreamer instead of textually.
...
llvm-svn: 84509
2009-10-19 18:03:08 +00:00
ee9399acaa
cleanup doFinalization -> EmitEndOfAsmFile.
...
llvm-svn: 84508
2009-10-19 17:59:19 +00:00
5ca7b345b9
PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions.
...
llvm-svn: 84506
2009-10-19 17:31:16 +00:00
033f01c922
Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
...
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.
llvm-svn: 84485
2009-10-19 11:00:58 +00:00
18df82a20c
Add support for matching shuffle patterns with palignr.
...
llvm-svn: 84459
2009-10-19 02:17:23 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
...
llvm-svn: 84431
2009-10-18 19:57:27 +00:00
936d87b39d
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
...
llvm-svn: 84425
2009-10-18 18:31:31 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
...
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
0b8db2dab7
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
...
llvm-svn: 84411
2009-10-18 06:27:36 +00:00
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
...
llvm-svn: 84326
2009-10-17 09:20:14 +00:00
8759585aba
Revert 84315 for now. Re-thinking the patch.
...
llvm-svn: 84321
2009-10-17 07:53:04 +00:00
0818d87ed1
Rename getFixedStack to getStackObject. The stack objects represented are not
...
necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
2009-10-17 06:22:26 +00:00
a3aaf85e23
Remove MallocInst from LLVM Instructions.
...
llvm-svn: 84299
2009-10-17 01:18:07 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
...
llvm-svn: 84273
2009-10-16 21:06:15 +00:00
ca019e704c
Update CMake file.
...
llvm-svn: 84252
2009-10-16 10:29:08 +00:00
89259d7929
Cleaned up some code. No functionality change.
...
llvm-svn: 84251
2009-10-16 08:58:34 +00:00
343d17d762
I am no spelling bee.
...
llvm-svn: 84250
2009-10-16 06:18:09 +00:00
03da4dba59
Enable post-alloc scheduling for all ARM variants except for Thumb1.
...
llvm-svn: 84249
2009-10-16 06:11:08 +00:00
8cd7c92613
Add comment.
...
llvm-svn: 84246
2009-10-16 05:33:58 +00:00
01404ecec7
Fix more NEON instruction encodings.
...
Patch by Johnny Chen.
llvm-svn: 84243
2009-10-16 03:58:44 +00:00
419160bd79
Revert svn r80498 and replace it with a different solution. The only problem
...
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
llvm-svn: 84218
2009-10-15 23:12:05 +00:00
49e417c52c
Dllexport stuff cleanup:
...
1. Emit external function type information for all COFF targets since it's
a feature of object format
2. Emit linker directives only for cygming (since this is ld-specific stuff)
llvm-svn: 84214
2009-10-15 22:36:18 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
...
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
4138b11c93
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
...
Patch by Johnny Chen.
llvm-svn: 84206
2009-10-15 21:57:47 +00:00
644de27659
Fix ARM memory operand parsing of post indexing with just a base register, that
...
is just "[Rn]" and no tailing comma with an offset, etc.
llvm-svn: 84205
2009-10-15 21:42:45 +00:00
2f9be50774
Fix a potential performance problem in placing ARM constant pools.
...
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
llvm-svn: 84202
2009-10-15 20:49:47 +00:00
146dcf2ab5
More bits of the ARM target assembler for llvm-mc, code added to parse labels
...
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
llvm-svn: 84201
2009-10-15 20:48:48 +00:00
e4a2117161
Remove X86Subtarget::IsLinux. It's no longer being used.
...
llvm-svn: 84200
2009-10-15 20:23:21 +00:00
74c35c126a
Add files Sanjiv forgot.
...
llvm-svn: 84196
2009-10-15 19:46:34 +00:00
a07cae65e3
Re-apply 84180 with the fixed test case.
...
llvm-svn: 84195
2009-10-15 19:26:25 +00:00
460ceae432
Move Blackfin intrinsics into the Target/Blackfin directory.
...
llvm-svn: 84194
2009-10-15 18:50:52 +00:00
923b5aa973
Clean up TargetIntrinsicInfo API. Add pure virtual methods.
...
llvm-svn: 84192
2009-10-15 18:49:26 +00:00
3b5bdd536b
Revert "Complete Rewrite of AsmPrinter, TargetObjectFile based on new
...
PIC16Section class", it breaks globals.ll.
llvm-svn: 84184
2009-10-15 15:02:14 +00:00
917db86b42
Complete Rewrite of AsmPrinter, TargetObjectFile based on new PIC16Section class
...
derived from MCSection.
llvm-svn: 84180
2009-10-15 10:10:43 +00:00
7357636091
Few changes to comply with new DebugInfo Metadata representation.
...
llvm-svn: 84179
2009-10-15 09:48:25 +00:00
68ead6c7a8
Be smarter about reusing constant pool entries.
...
llvm-svn: 84173
2009-10-15 05:52:29 +00:00
b4f2a85fe4
Fix another problem with ARM constant pools. Radar 7303551.
...
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
llvm-svn: 84172
2009-10-15 05:10:36 +00:00
cfcf6bc70d
Fix instruction encoding bits for NEON VPADAL.
...
Patch by Johnny Chen.
llvm-svn: 84146
2009-10-14 21:43:17 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
...
llvm-svn: 84144
2009-10-14 21:40:45 +00:00
94068707e1
Inst{11-8} for vshl should be 0b0101, not 0b1111.
...
Refs: A7-17 & A8-750.
Patch by Johnny Chen.
llvm-svn: 84131
2009-10-14 20:31:01 +00:00
1a791eedbf
Set instruction encoding bits 4 and 7 for ARM register-register and
...
register-shifted-register instructions. Patch by Johnny Chen.
llvm-svn: 84124
2009-10-14 19:00:24 +00:00
c350cdf3b3
Refactor code to select NEON VST intrinsics.
...
llvm-svn: 84122
2009-10-14 18:32:29 +00:00
12b4799787
Refactor code to select NEON VLD intrinsics.
...
llvm-svn: 84117
2009-10-14 17:28:52 +00:00
93117bc499
More refactoring. NEON vst lane intrinsics can share almost all the code for
...
vld lane intrinsics.
llvm-svn: 84110
2009-10-14 16:46:45 +00:00
4145e3ac8d
Refactor code for selecting NEON load lane intrinsics.
...
llvm-svn: 84109
2009-10-14 16:19:03 +00:00
0be8c2b0e3
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards
...
(for uses marked kill and defs marked dead) a few instructions in
addition to forwards. Also, increase the maximum number of instructions
to scan, as it appears to help in a fair number of cases.
llvm-svn: 84061
2009-10-14 00:08:59 +00:00
3a80daced0
Correct comment about ARM immediates using '#' not '$' and TODO for modifiers.
...
llvm-svn: 84055
2009-10-13 23:33:38 +00:00
d7ebfe3963
s/DebugLoc.CompileUnit/DebugLoc.Scope/g
...
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g
llvm-svn: 84054
2009-10-13 23:28:53 +00:00
b62d160b3c
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
...
by creating TargetConstants during instruction selection instead of during
legalization.
llvm-svn: 84042
2009-10-13 22:29:24 +00:00
f50799412c
More bits of the ARM target assembler for llvm-mc to parse immediates.
...
Also fixed a couple of coding style things that crept in. And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.
llvm-svn: 84040
2009-10-13 22:19:02 +00:00
1fdbe1152d
NEON VLD/VST are now fully implemented. For operations that expand to
...
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
llvm-svn: 84036
2009-10-13 21:55:24 +00:00
3b51560ae4
Revise ARM inline assembly memory operands to require the memory address to
...
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
llvm-svn: 84022
2009-10-13 20:50:28 +00:00
7460e0822f
Fix method name in comment, per Bob Wilson.
...
llvm-svn: 84017
2009-10-13 20:25:58 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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llvm-svn: 84009
2009-10-13 18:59:48 +00:00
f34311779c
Update CMake file (lexically order files).
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llvm-svn: 84008
2009-10-13 18:57:27 +00:00
453a06e3ac
Add some ARM instruction encoding bits.
...
Patch by Johnny Chen.
llvm-svn: 83983
2009-10-13 17:35:30 +00:00
d26a26ae7e
Fix regression introduced by r83894.
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llvm-svn: 83982
2009-10-13 17:29:13 +00:00
0bc673de0d
Fix a tab. Thanks to Johnny Chen for pointing it out.
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llvm-svn: 83973
2009-10-13 15:27:23 +00:00
11b32384f2
Fix two warnings about unused variables that are only used in assert() calls.
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llvm-svn: 83917
2009-10-12 22:51:49 +00:00
5b07a903d4
Delete a comment that makes no sense to me. The statement that moving a CPE
...
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb. Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.
llvm-svn: 83916
2009-10-12 22:49:05 +00:00
3f0b9b3db4
Fix a problem in the code where ARMAsmParser::ParseShift() second argument
...
should have been a pointer to a reference.
llvm-svn: 83915
2009-10-12 22:39:54 +00:00
3250e7769f
Change CreateNewWater method to return NewMBB by reference.
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llvm-svn: 83905
2009-10-12 21:39:43 +00:00
cc121aa750
Last week, ARMConstantIslandPass was failing to converge for the
...
MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now. Radar 7291928.
The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it. There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code. The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range. On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted. The second CPE had
been in range but the newly inserted entry pushed it too far away. Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range. Etc.
Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references. In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs. This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it. This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs. This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.
To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion. The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses. This is a very simple change to the code and should not cause
any significant degradation in the results.
llvm-svn: 83902
2009-10-12 21:23:15 +00:00
e4adae267e
Another minor clean-up.
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llvm-svn: 83897
2009-10-12 20:45:53 +00:00
196bf32ab0
Remove redundant parameter.
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llvm-svn: 83894
2009-10-12 20:37:23 +00:00
3a7326e705
Use early exit to reduce indentation.
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llvm-svn: 83874
2009-10-12 19:04:03 +00:00
3af34312d4
Change to return a value by reference.
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llvm-svn: 83873
2009-10-12 19:01:12 +00:00
c7a3cf4066
Add a typedef for an iterator.
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llvm-svn: 83872
2009-10-12 18:52:13 +00:00
06243d7bf2
Revert the kludge in 76703. I got a clean
...
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.
llvm-svn: 83871
2009-10-12 18:49:00 +00:00
a698d7ac3c
Don't forget to mark RAX as live-out of the function when arranging for
...
it to hold the address of an sret return value, for x86-64 ABI purposes.
Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.
llvm-svn: 83853
2009-10-12 16:36:12 +00:00
0840c823e4
Fix PR5087, patch by Jakub Staszak!
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llvm-svn: 83822
2009-10-12 04:22:44 +00:00
4b38ce9f25
Add missed mem-mem move patterns
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llvm-svn: 83812
2009-10-11 23:03:53 +00:00
415c3dc501
Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
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llvm-svn: 83811
2009-10-11 23:03:28 +00:00
6bce6bbf40
Implement 'm' memory operand properly
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llvm-svn: 83785
2009-10-11 19:14:21 +00:00
a58a3f930a
Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals.
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llvm-svn: 83784
2009-10-11 19:14:02 +00:00
3525a4a268
Implement asm printing for inline asm memory operands
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llvm-svn: 83783
2009-10-11 19:13:34 +00:00
5b8826b4da
It seems that OR operation does not affect status reg at all.
...
Remove impdef of SRW. This fixes PR4779
llvm-svn: 83739
2009-10-10 22:17:47 +00:00
1faa11521e
Remove a no-longer-necessary #include.
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llvm-svn: 83697
2009-10-10 00:36:09 +00:00
e919de5acf
Replace X86's CanRematLoadWithDispOperand by calling the target-independent
...
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.
llvm-svn: 83696
2009-10-10 00:34:18 +00:00
4a72f7ab53
Mark the LDR instruction with isReMaterializable, as it is rematerializable
...
when loading from an invariant memory location.
llvm-svn: 83688
2009-10-09 23:28:27 +00:00
f4eb6777e5
Add a const qualifier.
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llvm-svn: 83677
2009-10-09 22:09:05 +00:00
a2b99107c4
Added another bit of the ARM target assembler to llvm-mc to parse register
...
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
llvm-svn: 83673
2009-10-09 21:12:28 +00:00
7d9dffb413
Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
...
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.
llvm-svn: 83670
2009-10-09 20:35:19 +00:00
dd76bb23d1
Add basic infrastructure and x86 support for preserving MachineMemOperand
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information when unfolding memory references.
llvm-svn: 83656
2009-10-09 18:10:05 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
...
Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
222b86cd54
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
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llvm-svn: 83572
2009-10-08 20:43:22 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
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llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
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llvm-svn: 83565
2009-10-08 18:51:31 +00:00
02fda54e8f
Add missing names for the XCore specific LADD and LSUB nodes.
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llvm-svn: 83556
2009-10-08 17:14:57 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
534ea5ae32
Cleanup up unused R3LiveIn tracking.
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llvm-svn: 83522
2009-10-08 01:50:26 +00:00
c0615aa17f
Re-enable register scavenging in Thumb1 by default.
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llvm-svn: 83521
2009-10-08 01:46:59 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
456735c54b
reverting thumb1 scavenging default due to test failure while I figure out what's up.
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llvm-svn: 83501
2009-10-07 22:49:41 +00:00
e32fe29d29
Fix handling of x86 'R' constraint.
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llvm-svn: 83499
2009-10-07 22:47:20 +00:00
37cf79e5a6
Enable thumb1 register scavenging by default.
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llvm-svn: 83494
2009-10-07 22:26:14 +00:00
50820a2677
Add some instruction encoding bits for NEON load/store instructions.
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llvm-svn: 83490
2009-10-07 21:53:04 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
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llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
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llvm-svn: 83484
2009-10-07 20:30:08 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
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llvm-svn: 83482
2009-10-07 18:47:39 +00:00
ab3a9474d6
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
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llvm-svn: 83479
2009-10-07 18:09:32 +00:00
2207e5fc7b
Add another bit of the ARM target assembler to llvm-mc to parse registers
...
with writeback, things like "sp!", etc. Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.
llvm-svn: 83477
2009-10-07 18:01:35 +00:00
be8137b0b4
Replace TargetInstrInfo::isInvariantLoad and its target-specific
...
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
llvm-svn: 83475
2009-10-07 17:38:06 +00:00
6bbefc2f67
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
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llvm-svn: 83471
2009-10-07 17:24:55 +00:00
99e80228a9
Rearrange code for selecting vld2 intrinsics. No functionality change.
...
This is just to be more consistent with the forthcoming code for vld3/4.
llvm-svn: 83470
2009-10-07 17:23:09 +00:00
fa14dd430c
Add register-reuse to frame-index register scavenging. When a target uses
...
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
llvm-svn: 83467
2009-10-07 17:12:56 +00:00
75b59fb055
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
...
and register spills.
llvm-svn: 83435
2009-10-07 00:06:35 +00:00
febe39b488
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
...
operands. Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts. This is a work in progress.
llvm-svn: 83424
2009-10-06 22:26:42 +00:00
e6b778d5ff
Add codegen support for NEON vld2 operations on quad registers.
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llvm-svn: 83422
2009-10-06 22:01:59 +00:00
74b3d284f2
Use copyRegToReg hook to copy registers.
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llvm-svn: 83421
2009-10-06 22:01:15 +00:00
dc7d1ce575
Fix a comment typo.
...
Patch by Johnny Chen.
llvm-svn: 83407
2009-10-06 20:18:46 +00:00
10d3dc569b
Instead of printing unnecessary basic block labels as labels in
...
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
llvm-svn: 83392
2009-10-06 17:38:38 +00:00
692f6e7f9d
Remove xs1b predicate since it is no longer needed to differentiate betweem
...
xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
d7b887410d
Remove xs1a subtarget. xs1a is a preproduction device used in
...
early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00
29e8555056
Default to the xs1b subtarget
...
llvm-svn: 83380
2009-10-06 15:41:52 +00:00
051454a16f
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
...
llvm-svn: 83363
2009-10-06 02:19:11 +00:00
2dfb5da6bb
In Thumb1, the register scavenger is not always able to use an emergency
...
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
llvm-svn: 83336
2009-10-05 22:30:23 +00:00
2728569a38
Remove explicit enum integer values. They don't appear to be needed, and
...
they make it less convenient to add new entries.
llvm-svn: 83308
2009-10-05 15:52:08 +00:00
774149a878
Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP
...
is used in an operand which requires GR64_NOREX.
llvm-svn: 83307
2009-10-05 15:42:08 +00:00
fdd8790718
strength reduce a ton of type equality tests to check the typeid (Through
...
the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
llvm-svn: 83297
2009-10-05 05:54:46 +00:00
d76b9b766c
Add a comment to describe letters used in multiclass name suffixes.
...
llvm-svn: 83257
2009-10-03 04:44:16 +00:00
a9abf57409
Fix encoding problem for VMLS instruction.
...
Thanks to Johnny Chen for pointing this out!
llvm-svn: 83256
2009-10-03 04:41:21 +00:00
32a47ea7b6
getFunctionAlignment should return log2 alignment.
...
llvm-svn: 83242
2009-10-02 06:57:25 +00:00
b659dff4eb
Forgot about ARM::tPUSH. It also has a new writeback operand.
...
llvm-svn: 83237
2009-10-02 05:03:07 +00:00
2dcee28a61
Move load / store multiple before post-alloc scheduling.
...
llvm-svn: 83236
2009-10-02 04:57:15 +00:00
1cc6dd97da
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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llvm-svn: 83218
2009-10-01 22:19:57 +00:00
9a051a5922
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
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llvm-svn: 83215
2009-10-01 21:46:35 +00:00
6f012d83f2
ARM::tPOP and tPOP_RET each has an extra writeback operand now.
...
llvm-svn: 83214
2009-10-01 20:54:53 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
4bcd523acb
Update ARM JIT emitter to account for ld/st multiple changes.
...
llvm-svn: 83192
2009-10-01 01:39:21 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
e0709cfc92
Use MachineInstr as an processDebugLoc() argument.
...
This will allow processDebugLoc() to handle scopes for DWARF debug info.
llvm-svn: 83183
2009-09-30 23:12:50 +00:00
b2120755a2
Use OutStreamer.SwitchSection instead of writing out textual section directives.
...
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
llvm-svn: 83178
2009-09-30 22:25:37 +00:00
b633d7a665
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
...
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
llvm-svn: 83176
2009-09-30 22:06:26 +00:00
64c8d5a004
Fix a comment typo.
...
llvm-svn: 83174
2009-09-30 21:44:42 +00:00
699702e0a8
The AsmPrinter base class contains a DwarfWriter member, so there's no need
...
for derived AsmPrinters to add another one. In some cases, fixing this
removes the need to override the doInitialization method.
llvm-svn: 83170
2009-09-30 21:24:45 +00:00
a2fe1a6811
Clarify comment phrasing.
...
llvm-svn: 83148
2009-09-30 15:23:38 +00:00
ce5a8ca3ef
Add a option which would move ld/st multiple pass before post-alloc scheduling.
...
llvm-svn: 83145
2009-09-30 08:53:01 +00:00
70ce8a03b1
When checking whether we need to reserve a register for the scavenger,
...
the size of the saved frame pointer needs to be taken into account.
llvm-svn: 83136
2009-09-30 01:43:29 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
20e5f5ed79
For Darwin, emit all the text section directives together before the dwarf
...
section directives. This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations. Radar 7255355.
llvm-svn: 83127
2009-09-30 00:23:42 +00:00
17199b56b0
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
...
llvm-svn: 83122
2009-09-30 00:10:16 +00:00
fa6847f099
minor cleanup and add clarifying comment
...
llvm-svn: 83117
2009-09-29 23:17:20 +00:00
b296942f6d
Remove std::string uses from DebugInfo interface.
...
llvm-svn: 83083
2009-09-29 18:40:58 +00:00
139c3dba53
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
...
llvm-svn: 83058
2009-09-29 07:07:30 +00:00
5264202a38
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
...
slot for the register scavenger when compiling Thumb1 functions.
llvm-svn: 83023
2009-09-28 22:08:06 +00:00
Evan Cheng