6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
...
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
...
llvm-svn: 88734
2009-11-14 01:50:00 +00:00
ff0302489b
The instruction pointer %RIP is a reserved register on x86_64.
...
llvm-svn: 88705
2009-11-13 21:56:01 +00:00
659c1a9d78
Move DebugInfo checks into EmitComments and remove them from
...
target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
llvm-svn: 88697
2009-11-13 21:34:57 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
...
llvm-svn: 88682
2009-11-13 19:52:48 +00:00
a03b5b44fc
Support fp64 immediate zero, this fixes only part of PR5445
...
because the testcase is triggering one more bug.
llvm-svn: 88674
2009-11-13 18:49:59 +00:00
5f4eecf961
Adjust isConstantSplat to allow for big-endian targets.
...
PPC is such a target; make it work.
llvm-svn: 87060
2009-11-13 01:45:18 +00:00
46a524c3e8
Block renumbering
...
llvm-svn: 87056
2009-11-13 01:19:24 +00:00
969910b3e8
use lower case for readability
...
llvm-svn: 87054
2009-11-13 01:17:22 +00:00
2f4c37425b
Fix a bootstrap failure.
...
Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands. This uses a heuristic so it isn't reliable for correctness.
llvm-svn: 87047
2009-11-13 00:29:53 +00:00
be851acfb0
Make the MachineFunction argument of getFrameRegister const.
...
This also fixes a build error.
llvm-svn: 87027
2009-11-12 21:00:03 +00:00
70fdd57dc1
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a
...
machine instruction loads or stores from/to a stack slot. Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand). This helps AsmPrinter determine when
to print a spill/reload comment.
This is only a hint since we may not be able to figure this out in all
cases. As such, it should not be relied upon for correctness.
Implement for X86. Return false by default for other architectures.
llvm-svn: 87026
2009-11-12 20:55:29 +00:00
1fbe054450
Add a bool flag to StackObjects telling whether they reference spill
...
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
2009-11-12 20:49:22 +00:00
68e4945c03
Add compare_lower and equals_lower methods to StringRef. Switch all users of
...
StringsEqualNoCase (from StringExtras.h) to it.
llvm-svn: 87020
2009-11-12 20:36:59 +00:00
5d57714e6c
Update TB[BH] layout optimization. Add support for moving the target block
...
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
llvm-svn: 86999
2009-11-12 17:25:07 +00:00
e129dd311e
Use table to separate opcode from operands.
...
llvm-svn: 86965
2009-11-12 07:16:34 +00:00
15b80e4a9f
isLegalICmpImmediate should take a signed integer; code clean up.
...
llvm-svn: 86964
2009-11-12 07:13:11 +00:00
6385ea7c4e
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
...
llvm-svn: 86945
2009-11-12 03:28:35 +00:00
626d49f684
A real solution for the first part of PR5445
...
llvm-svn: 86895
2009-11-11 23:09:33 +00:00
3d3c24a82c
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
...
llvm-svn: 86858
2009-11-11 19:05:52 +00:00
d576d66d91
Do jump table adjustment before constant island allocation
...
llvm-svn: 86857
2009-11-11 19:04:24 +00:00
9fd22f68f2
Set isBarrier = 1 on return instructions, as they are control barriers.
...
llvm-svn: 86851
2009-11-11 18:11:07 +00:00
d2a0f80ede
Use a tab in INT3's asm string, for consistency.
...
llvm-svn: 86850
2009-11-11 18:07:16 +00:00
7a09964e81
another const prop failure.
...
llvm-svn: 86848
2009-11-11 17:54:02 +00:00
539bdf0487
add a note
...
llvm-svn: 86847
2009-11-11 17:51:27 +00:00
8d92ec45c7
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
...
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
llvm-svn: 86791
2009-11-11 02:47:19 +00:00
bc299f0092
llvm-gcc/clang don't (won't?) need this hack.
...
llvm-svn: 86769
2009-11-11 00:28:38 +00:00
0169fd7c62
add a note
...
llvm-svn: 86756
2009-11-10 23:47:45 +00:00
8ff26038ef
I did this a week or two ago
...
llvm-svn: 86754
2009-11-10 23:40:49 +00:00
de8d418ac3
Don't mark conditional branch instructions as control barriers.
...
llvm-svn: 86732
2009-11-10 22:16:57 +00:00
fc9469f311
Modify how the prologue encoded the "move" information for the FDE. GCC
...
generates a sequence similar to this:
__Z4funci:
LFB2:
mflr r0
LCFI0:
stmw r30,-8(r1)
LCFI1:
stw r0,8(r1)
LCFI2:
stwu r1,-80(r1)
LCFI3:
mr r30,r1
LCFI4:
where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:
Leh_func_begin1:
mflr r0
stw r31, 20(r1)
stw r0, 8(r1)
Llabel1:
stwu r1, -80(r1)
Llabel2:
mr r31, r1
Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.
llvm-svn: 86729
2009-11-10 22:14:04 +00:00
e034867587
Change Thumb1 address mode printing, instead of
...
[r0, #2 * 4]
Now
[r0, #8 ]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
llvm-svn: 86707
2009-11-10 19:48:13 +00:00
e6548f4106
Add a comment.
...
llvm-svn: 86706
2009-11-10 19:44:56 +00:00
b9415c7d9a
Add a monstrous hack to improve X86ISelDAGToDAG compile time.
...
- Force NDEBUG on in any Release build. This drops the compile time to ~100s
from ~600s, in Release mode.
- This may just be a temporary workaround, I don't know the true nature of the
gcc-4.2 compile time performance problem.
llvm-svn: 86695
2009-11-10 18:24:37 +00:00
05671ea10a
Fix PR5445
...
llvm-svn: 86651
2009-11-10 02:35:13 +00:00
b40d3f76a0
Fix DenseMap iterator constness.
...
This patch forbids implicit conversion of DenseMap::const_iterator to
DenseMap::iterator which was possible because DenseMapIterator inherited
(publicly) from DenseMapConstIterator. Conversion the other way around is now
allowed as one may expect.
The template DenseMapConstIterator is removed and the template parameter
IsConst which specifies whether the iterator is constant is added to
DenseMapIterator.
Actually IsConst parameter is not necessary since the constness can be
determined from KeyT but this is not relevant to the fix and can be addressed
later.
Patch by Victor Zverovich!
llvm-svn: 86636
2009-11-10 01:02:17 +00:00
0d412c2528
Fixed to address code review. No functional changes.
...
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
...
llvm-svn: 86628
2009-11-10 00:15:47 +00:00
2524b04d0e
Now that the default is 'enabled,' a separate command line option for ARM is
...
not necessary.
llvm-svn: 86621
2009-11-09 23:11:45 +00:00
1218b804fb
Enable dynamic stack realignment by default.
...
llvm-svn: 86604
2009-11-09 22:32:40 +00:00
55d3480769
Set dynamic stack realignment to real values.
...
llvm-svn: 86602
2009-11-09 22:32:03 +00:00
787997f77e
Similar to r86588, but for Darwin this time.
...
llvm-svn: 86592
2009-11-09 21:45:26 +00:00
7307bff420
The jump table was being generated before the end label for exception handling
...
was generated. This caused code like this:
## The asm code for the function
.section __TEXT,__const
.align 2
lJTI11_0:
LJTI11_0:
.long LBB11_16
.long LBB11_4
.long LBB11_5
.long LBB11_6
.long LBB11_7
.long LBB11_8
.long LBB11_9
.long LBB11_10
.long LBB11_11
.long LBB11_12
.long LBB11_13
.long LBB11_14
Leh_func_end11: ## <---now in the wrong section!
The `Leh_func_end11' would then end up in the wrong section, causing the
resulting EH frame information to be wrong:
__ZL11CheckRightsjPKcbRbRP6NSData.eh:
.set Lset500eh,Leh_frame_end11-Leh_frame_begin11
.long Lset500eh ; Length of Frame Information Entry
Leh_frame_begin11:
.long Leh_frame_begin11-Leh_frame_common
.long Leh_func_begin11-.
.set Lset501eh,Leh_func_end11-Leh_func_begin11
.long Lset501eh ; FDE address range
`Lset501eh' is now something huge instead of the real value.
The X86 back-end generates the jump table after the EH information is
emitted. Do the same here.
llvm-svn: 86588
2009-11-09 21:20:14 +00:00
ad95414c26
Work around assembler not recognizing #0.0 form immediate for vmcp
...
llvm-svn: 86548
2009-11-09 15:27:51 +00:00
8dd7c54a42
Fix PR5149.
...
http://llvm.org/bugs/show_bug.cgi?id=5149
llvm-svn: 86543
2009-11-09 14:27:49 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
700c4ab3f9
Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
...
llvm-svn: 86471
2009-11-08 15:33:12 +00:00
e92c508764
Move OR patterns upper to all logical stuff. No functionality change.
...
llvm-svn: 86470
2009-11-08 15:32:44 +00:00
a404d61c8e
Some nice peephole patterns. Based on patch by Brian Lucas!
...
llvm-svn: 86469
2009-11-08 15:32:28 +00:00
fd9a893cab
Print tab before operand of jcc
...
llvm-svn: 86468
2009-11-08 15:32:11 +00:00
4ca8d3a6a6
Fix invalid operand updates & implement post-inc memory operands
...
llvm-svn: 86466
2009-11-08 14:27:38 +00:00
eb8692cff9
Throw an error when stack realignment stuff fails instead of silent
...
code miscompilation
llvm-svn: 86463
2009-11-08 12:58:40 +00:00
295f266370
Make TargetData::getStringRepresentation spit out native integer types,
...
this gives llvm-gcc generated modules the right data.
llvm-svn: 86435
2009-11-08 02:32:01 +00:00
a15c3b7124
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
...
llvm-svn: 86425
2009-11-08 00:27:19 +00:00
fe864425cb
Refactor code.
...
llvm-svn: 86423
2009-11-08 00:15:23 +00:00
3a313df69b
x86 vector shuffle cleanup/fixes:
...
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
llvm-svn: 86415
2009-11-07 23:17:15 +00:00
4e9f379554
80-column cleanup of file header comments
...
llvm-svn: 86408
2009-11-07 22:00:39 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
...
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
b9397262b7
Improve tail call elimination to handle the switch statement.
...
llvm-svn: 86403
2009-11-07 21:10:15 +00:00
8b5278a466
t2ldrpci_pic can be used for blockaddress as well.
...
llvm-svn: 86400
2009-11-07 19:40:04 +00:00
8714348afd
indicate what the native integer types for the target are.
...
Please verify.
llvm-svn: 86397
2009-11-07 19:07:32 +00:00
cf84ab5043
First try of the post-inc operands handling... Not fully worked, though :(
...
llvm-svn: 86386
2009-11-07 17:15:25 +00:00
d3c8319f48
Add some dummy support for post-incremented loads
...
llvm-svn: 86385
2009-11-07 17:15:06 +00:00
f93bb39b03
Add 8 bit libcalls and make use of them for msp430
...
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
e61e0b9a74
Add few pseudo-source-values
...
llvm-svn: 86383
2009-11-07 17:13:57 +00:00
2a88785685
Initial support for addrmode handling. Tests by Brian Lucas!
...
llvm-svn: 86382
2009-11-07 17:13:35 +00:00
1bbc8d2a86
Some preliminary variable asmprinting
...
llvm-svn: 86381
2009-11-07 17:12:58 +00:00
3b7c712e9e
Use '.L' for global private prefix (as mspgcc)
...
llvm-svn: 86380
2009-11-07 17:12:38 +00:00
e04fa15cb3
Drop old asmprinter stuff
...
llvm-svn: 86379
2009-11-07 17:12:21 +00:00
226467d6a6
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
a381effe72
add the ability for TargetData to return information about legal integer
...
datatypes on a given CPU. This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA. See also "Adding
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.
Comments welcome.
llvm-svn: 86370
2009-11-07 09:35:34 +00:00
91f9582fe1
more cleanup.
...
llvm-svn: 86369
2009-11-07 09:23:04 +00:00
d82510e109
add some missing #includes
...
llvm-svn: 86367
2009-11-07 09:20:54 +00:00
f819398067
rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings.
...
llvm-svn: 86366
2009-11-07 09:13:23 +00:00
db5f24ce77
Make the need-stub variables accurate and consistent. In the case of
...
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
llvm-svn: 86363
2009-11-07 08:51:52 +00:00
bd05185ef1
Fix a couple of shuffle patterns to use movhlps instead
...
of movhps as the constraint. Changes optimizations so
update testcases as appropriate as well.
llvm-svn: 86360
2009-11-07 08:45:53 +00:00
5321dd8823
Fixed Overload table bug noticed by Jakob
...
llvm-svn: 86332
2009-11-07 04:07:33 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
50dddc8b07
Update CMake file.
...
llvm-svn: 86325
2009-11-07 03:26:59 +00:00
07119737aa
Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
...
llvm-svn: 86324
2009-11-07 02:11:54 +00:00
3467dcb12d
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
...
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
2009-11-07 00:54:36 +00:00
79d70e3e65
80-columns
...
llvm-svn: 86310
2009-11-07 00:13:30 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
9df3acf486
Honour subreg machine operands during asmprinting
...
llvm-svn: 86303
2009-11-06 23:45:15 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
408aa56fb5
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
...
llvm-svn: 86294
2009-11-06 22:24:13 +00:00
ad36e8aceb
Pass StringRef by value.
...
llvm-svn: 86251
2009-11-06 10:58:06 +00:00
ee8afcc59d
Factor out the printing of the leading tab into printInlineAsm.
...
llvm-svn: 86199
2009-11-06 00:04:54 +00:00
006f9353e1
Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's
...
implicit zero-extend.
llvm-svn: 86196
2009-11-05 23:53:08 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
...
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
06c26d982e
add a note from PR5313
...
llvm-svn: 86146
2009-11-05 18:19:19 +00:00
1a58236c2b
Reintroduce support for overloading target intrinsics
...
llvm-svn: 86114
2009-11-05 03:19:08 +00:00
31569240c6
Grammar.
...
llvm-svn: 86068
2009-11-04 23:20:40 +00:00
5833df9bde
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
...
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
llvm-svn: 86064
2009-11-04 23:11:07 +00:00
2c7fd8f1db
If a function has no stack frame at all, dynamic realignment isn't necessary.
...
llvm-svn: 86057
2009-11-04 22:41:51 +00:00
cc58cc1d56
dynamic stack realignment necessitates scanning the floating point callee-
...
saved instructions even if no stack adjustment for those saves is needed.
llvm-svn: 86056
2009-11-04 22:41:00 +00:00
f84f7105f7
Add PowerPC codegen for indirect branches.
...
llvm-svn: 86050
2009-11-04 21:31:18 +00:00
c7cfc94bcc
Print out an informative comment for KILL instructions.
...
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
llvm-svn: 86041
2009-11-04 19:24:37 +00:00
c63943018f
The .n suffix must go after the predicate.
...
llvm-svn: 86019
2009-11-04 07:38:48 +00:00
3f1a92468a
Use ldr.n to workaround a darwin assembler bug.
...
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
76a4774a0d
Move subtarget check upper for NEON reg-reg fixup pass.
...
llvm-svn: 85914
2009-11-03 18:46:11 +00:00
31c2f4701b
Trim unnecessary include.
...
llvm-svn: 85878
2009-11-03 07:08:08 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
...
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
23c009f125
Clean up copyRegToReg.
...
llvm-svn: 85870
2009-11-03 05:51:39 +00:00
9e9079371c
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
...
llvm-svn: 85869
2009-11-03 05:50:57 +00:00
187cb4f493
Update CMake file.
...
llvm-svn: 85861
2009-11-03 04:14:12 +00:00
d195f9e5c3
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
...
llvm-svn: 85850
2009-11-03 01:04:26 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
b389f2a04d
Revert previous change to a comment. The BlockAddresses go in the
...
constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
d9dfc2e752
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
...
have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
4c00a524eb
Hyphenate some comments.
...
llvm-svn: 85808
2009-11-02 17:10:37 +00:00
433ab09ca3
Add support for BlockAddress values in ARM constant pools.
...
llvm-svn: 85806
2009-11-02 16:59:06 +00:00
e90a4aa703
Prune unnecessary include.
...
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
115cfc07d5
These are done / no longer care.
...
llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
...
llvm-svn: 85797
2009-11-02 07:51:19 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
...
llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1a4492be97
Fix a couple more places where we are creating ld / st instructions without memoperands.
...
llvm-svn: 85746
2009-11-01 22:04:35 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
...
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
...
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
...
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
8be42bd09f
Updates to the ARM target assembler for llvm-mc per review comments from
...
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
llvm-svn: 85632
2009-10-30 22:55:57 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
...
llvm-svn: 85624
2009-10-30 22:22:46 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
...
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
6b00f4b7a8
Fix a comment.
...
llvm-svn: 85610
2009-10-30 20:13:25 +00:00
ab7c709f43
This fixes functions like
...
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
f7c4299312
Initial x86 support for BlockAddresses.
...
llvm-svn: 85557
2009-10-30 01:28:02 +00:00
8578068302
Dial back the realignment a bit.
...
llvm-svn: 85546
2009-10-30 00:08:40 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
...
realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
...
I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
...
llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
...
llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
...
llvm-svn: 85381
2009-10-28 06:55:03 +00:00
f64db3e1d0
X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes.
...
llvm-svn: 85379
2009-10-28 06:30:34 +00:00
a91a563530
Previously, all operands to Constant were themselves constant.
...
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.
llvm-svn: 85375
2009-10-28 05:14:34 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
...
llvm-svn: 85362
2009-10-28 01:44:26 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
...
llvm-svn: 85361
2009-10-28 01:43:28 +00:00
9c6bc1f563
Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
...
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
llvm-svn: 85357
2009-10-28 00:55:57 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
...
llvm-svn: 85355
2009-10-28 00:37:03 +00:00
d04cb6d0fa
rename indbr -> indirectbr to appease the residents of #llvm.
...
llvm-svn: 85351
2009-10-28 00:19:10 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
...
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
2e5198ff09
Add new note.
...
llvm-svn: 85341
2009-10-27 23:30:07 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
...
llvm-svn: 85335
2009-10-27 22:52:29 +00:00
fd2730ee8c
Move and clarify note.
...
llvm-svn: 85334
2009-10-27 22:48:31 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
...
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
2974f63cb5
Note corrected.
...
llvm-svn: 85332
2009-10-27 22:43:24 +00:00
cd4d148040
Modify note.
...
llvm-svn: 85331
2009-10-27 22:40:45 +00:00
a205402c16
Add a note.
...
llvm-svn: 85329
2009-10-27 22:34:43 +00:00
e8628a0206
cppbackend support for indbr
...
llvm-svn: 85312
2009-10-27 21:24:48 +00:00
42c979e8d3
CBE support for indbr.
...
llvm-svn: 85311
2009-10-27 21:21:06 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
...
llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
...
BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
...
llvm-svn: 85281
2009-10-27 19:56:55 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
...
instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
...
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
a789f17ffc
Remove unnecessary gotos to fall-thru successors.
...
llvm-svn: 85257
2009-10-27 17:40:24 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
...
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
fb22a85baf
apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :(
...
llvm-svn: 85252
2009-10-27 17:01:03 +00:00
d90d169f9d
Correctly align double arguments in the stack.
...
llvm-svn: 85235
2009-10-27 14:09:44 +00:00
538984c1c3
Now VFP instructions.
...
llvm-svn: 85186
2009-10-27 00:20:49 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85178
2009-10-26 23:45:59 +00:00
de5ad42aa1
Remove FreeInst.
...
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.
llvm-svn: 85176
2009-10-26 23:43:48 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
...
bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
...
Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
...
bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
ce8f626f82
Update CMake files.
...
llvm-svn: 85161
2009-10-26 22:06:01 +00:00
0ae1b2961d
Revert r85134, it breaks mingw build
...
llvm-svn: 85138
2009-10-26 18:40:24 +00:00
752aea6513
Make PIC16 overlay a loadable pass.
...
llvm-svn: 85134
2009-10-26 18:22:59 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
56869f22c4
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
...
direct inclusion edge from System to Support.
llvm-svn: 85086
2009-10-26 01:35:46 +00:00
5bde1cbd93
of -> or
...
llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
...
llvm-svn: 85064
2009-10-25 18:55:46 +00:00
b18a46806b
Reapply 85006 with a minor fix.
...
llvm-svn: 85052
2009-10-25 08:14:11 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
...
llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
...
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
13b8b56dd4
this is done.
...
llvm-svn: 85041
2009-10-25 06:17:51 +00:00
54d7179a25
Remove ICmpInst::isSignedPredicate which was a reimplementation
...
CmpInst::isSigned.
llvm-svn: 85037
2009-10-25 05:20:17 +00:00
9e8d42f295
Revert back 85006 for now as it breaks PIC16 tests.
...
llvm-svn: 85008
2009-10-24 18:19:41 +00:00
055c3305a1
Adding support for placing global objects in shared data memory.
...
llvm-svn: 85006
2009-10-24 18:02:44 +00:00
46ed1f8341
80 col violation.
...
llvm-svn: 84986
2009-10-24 02:07:42 +00:00
e2871d69db
Restrict Thumb1 register allocation to low registers, even for instructions that
...
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
llvm-svn: 84982
2009-10-24 00:19:24 +00:00
22b2c011f9
FIXME no longer applies. R12 and R3 are available for allocation
...
llvm-svn: 84977
2009-10-23 23:07:42 +00:00
851193b873
some stuff is done, we still have constantexpr simplification to do.
...
llvm-svn: 84943
2009-10-23 07:00:55 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
...
llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
c77f8634e5
Shift art to the right to keep GCC from complaining about multi-line comments.
...
llvm-svn: 84849
2009-10-22 09:28:49 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
943f4f41f2
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
...
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
5457a96b63
Trim more includes.
...
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
344fcd9d61
Trim include.
...
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
1448799377
fix warning.
...
llvm-svn: 84826
2009-10-22 03:42:27 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f1ad2c618a
Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
...
Yay for ASCII graphics!
llvm-svn: 84808
2009-10-22 00:16:00 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
...
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
b45d621ab1
Revert r84764, it breaks mingw build
...
llvm-svn: 84783
2009-10-21 21:15:18 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
9e92857b38
Add DAG printing for RMW stuff debugging
...
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
...
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
5399c2d05e
Implement branch folding
...
llvm-svn: 84774
2009-10-21 19:17:18 +00:00
2983dcb1f2
Cosmetic changes, no functionality changes
...
llvm-svn: 84773
2009-10-21 19:16:49 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
c5804f3cb6
Build shared lib instead of an archive.
...
llvm-svn: 84764
2009-10-21 17:27:23 +00:00
47ea743618
Add a pass to overlay pic16 data sections for function frame and automatic
...
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.
llvm-svn: 84753
2009-10-21 10:42:44 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
175d04c90f
tidy
...
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
bc69313909
IPSCCP is missing stuff.
...
llvm-svn: 84725
2009-10-21 01:10:37 +00:00
7099d0c19c
Add note
...
llvm-svn: 84713
2009-10-21 00:14:15 +00:00
e43af4a085
Be crazy and assert in case of unsupported modifier passed.
...
llvm-svn: 84712
2009-10-21 00:13:58 +00:00
11074fa73e
Handle external symbols
...
llvm-svn: 84711
2009-10-21 00:13:42 +00:00
cc55b9086d
Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting.
...
llvm-svn: 84710
2009-10-21 00:13:25 +00:00
94ba9c27b0
Add basic block operands & jump kinds
...
llvm-svn: 84709
2009-10-21 00:13:05 +00:00
8a06a4e5c8
Ignore all implicit reg operands
...
llvm-svn: 84708
2009-10-21 00:12:44 +00:00
196b0e5431
Add a workaround for different memops prefixes
...
llvm-svn: 84707
2009-10-21 00:12:27 +00:00
4e32bff382
Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries
...
llvm-svn: 84706
2009-10-21 00:12:08 +00:00
7fbc0a50d5
Add simple operand printing stuff
...
llvm-svn: 84704
2009-10-21 00:11:27 +00:00
6e78029d82
Add experimental MSP430 MCInstLowering stuff
...
llvm-svn: 84703
2009-10-21 00:11:08 +00:00
daaa2f0c31
Wire up MSP430 printMCInst() method
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llvm-svn: 84702
2009-10-21 00:10:47 +00:00
b6e2e4fd50
Add MSP430 InstPrinter stub
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llvm-svn: 84701
2009-10-21 00:10:30 +00:00
13de81ac40
Use proper target data
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llvm-svn: 84700
2009-10-21 00:10:00 +00:00
a470eac6a1
Fix -Asserts warning.
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llvm-svn: 84687
2009-10-20 22:10:05 +00:00
cccf5084a3
Disable by default while debugging
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llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
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llvm-svn: 84664
2009-10-20 20:19:50 +00:00
3d9d78463c
Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.
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llvm-svn: 84652
2009-10-20 18:14:49 +00:00
4a43e3068d
Make TranslateX86CC return COND_INVALID instead of aborting when it
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encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
llvm-svn: 84640
2009-10-20 16:22:37 +00:00
Evan Cheng