0de0ce11d8
Revert r91623 to unbreak the buildbots.
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llvm-svn: 91632
2009-12-17 22:44:34 +00:00
e43b403c87
Remove an unused option.
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llvm-svn: 91623
2009-12-17 21:23:58 +00:00
50272752fa
finish cleaning up StructLayoutMap.
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llvm-svn: 91612
2009-12-17 20:00:21 +00:00
798493285c
In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
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incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.
llvm-svn: 91602
2009-12-17 15:31:52 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
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llvm-svn: 91571
2009-12-16 23:36:52 +00:00
30f2ac714b
Silence a clang warning about the deprecated (but perfectly reasonable in
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context) increment-of-bool idiom.
llvm-svn: 91564
2009-12-16 20:31:50 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
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llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
1be6286028
Re-enable 91381 with fixes.
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llvm-svn: 91489
2009-12-16 00:53:11 +00:00
826ca5630e
Every anonymous namespace is different. Caught by clang++.
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llvm-svn: 91481
2009-12-16 00:15:28 +00:00
e0d8e14e11
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
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remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
llvm-svn: 91464
2009-12-15 22:42:46 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
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llvm-svn: 91434
2009-12-15 17:24:14 +00:00
b3032962ef
Fix an encoding bug.
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llvm-svn: 91417
2009-12-15 06:49:02 +00:00
792f0913ee
For fastcc on x86, let ECX be used as a return register after EAX and EDX
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llvm-svn: 91410
2009-12-15 03:27:52 +00:00
fcb5453dc7
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
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llvm-svn: 91405
2009-12-15 03:07:11 +00:00
0e8b9e32d1
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
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llvm-svn: 91381
2009-12-15 00:53:42 +00:00
ea8f6e31a0
nand atomic requires opposite operand ordering
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llvm-svn: 91371
2009-12-15 00:12:35 +00:00
cecad35728
Fix integer cast code to handle vector types.
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llvm-svn: 91362
2009-12-14 23:40:38 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
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between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
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llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
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llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
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llvm-svn: 91327
2009-12-14 21:01:46 +00:00
57ccc19617
Thumb2 atomic operations
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llvm-svn: 91321
2009-12-14 20:14:59 +00:00
726e452ccb
fix an obvious bug found by clang++ and collapse a redundant if.
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Here's the diagnostic from clang:
/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
printConstant(gv);
^
1 diagnostic generated.
llvm-svn: 91318
2009-12-14 19:34:32 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
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llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
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llvm-svn: 91310
2009-12-14 18:56:47 +00:00
3cdb555e0f
whitespace
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llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
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llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
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llvm-svn: 91284
2009-12-14 17:02:55 +00:00
277381f69a
Whitespace changes, comment clarification. No functional changes.
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llvm-svn: 91274
2009-12-14 06:51:19 +00:00
8f3c70e909
atomic binary operations up to 32-bits wide.
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llvm-svn: 91260
2009-12-14 04:22:04 +00:00
45800ce646
Do not allow uninitialize access during debug printing
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llvm-svn: 91232
2009-12-13 01:00:32 +00:00
96cf7f42b0
More info on this transformation.
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llvm-svn: 91230
2009-12-12 23:23:43 +00:00
8eada9f580
Remove some stuff that's already implemented. Also, remove the note about
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merging x >u 5 and x <s 20 because it's impossible to implement.
llvm-svn: 91228
2009-12-12 21:41:48 +00:00
26fdd7265b
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
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llvm-svn: 91223
2009-12-12 20:03:14 +00:00
d8f320947f
Implement variable-width shifts.
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No testcase yet - it seems we're exposing generic codegen bugs.
llvm-svn: 91221
2009-12-12 18:55:37 +00:00
3974c8de51
Add comment about potential partial register stall.
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llvm-svn: 91220
2009-12-12 18:55:26 +00:00
6d6eaafa8c
Fix an obvious bug. No test case since LEA16r is not being used.
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llvm-svn: 91219
2009-12-12 18:51:56 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
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just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
e27e028cdd
Lower setcc branchless, if this is profitable.
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Based on the patch by Brian Lucas!
llvm-svn: 91175
2009-12-11 23:01:29 +00:00
1d459e4937
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
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llvm-svn: 91158
2009-12-11 21:31:27 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
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llvm-svn: 91150
2009-12-11 20:29:53 +00:00
fc51282cbe
Honour setHasCalls() set from isel.
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This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
2009-12-11 19:39:55 +00:00
098bd1bbea
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
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llvm-svn: 91143
2009-12-11 19:37:26 +00:00
afdddaed55
Update properties.
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llvm-svn: 91140
2009-12-11 18:52:41 +00:00
766a73fb04
Add support to 3-addressify 16-bit instructions.
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llvm-svn: 91104
2009-12-11 06:01:48 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
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llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
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llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
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llvm-svn: 91003
2009-12-10 00:11:09 +00:00
493b882f80
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
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vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-09 21:00:30 +00:00
Jeffrey Yasskin