Commit Graph

289234 Commits

Author SHA1 Message Date
Artem Dergachev e603e076f5 [analyzer] pr36458: Fix retrieved value cast for symbolic void pointers.
C allows us to write any bytes into any memory region. When loading weird bytes
from memory regions of known types, the analyzer is required to make sure that
the loaded value makes sense by casting it to an appropriate type.

Fix such cast for loading values that represent void pointers from non-void
pointer type places.

Differential Revision: https://reviews.llvm.org/D46415

llvm-svn: 331562
2018-05-04 22:11:12 +00:00
Artem Dergachev 806486c781 [analyzer] pr18953: Split C++ zero-initialization from default initialization.
The bindDefault() API of the ProgramState allows setting a default value
for reads from memory regions that were not preceded by writes.

It was used for implementing C++ zeroing constructors (i.e. default constructors
that boil down to setting all fields of the object to 0).

Because differences between zeroing consturctors and other forms of default
initialization have been piling up (in particular, zeroing constructors can be
called multiple times over the same object, probably even at the same offset,
requiring a careful and potentially slow cleanup of previous bindings in the
RegionStore), we split the API in two: bindDefaultInitial() for modeling
initial values and bindDefaultZero() for modeling zeroing constructors.

This fixes a few assertion failures from which the investigation originated.

The imperfect protection from both inability of the RegionStore to support
binding extents and lack of information in ASTRecordLayout has been loosened
because it's, well, imperfect, and it is unclear if it fixing more than it
was breaking.

Differential Revision: https://reviews.llvm.org/D46368

llvm-svn: 331561
2018-05-04 21:56:51 +00:00
Craig Topper 2cd09d017a [X86] Correct the attributes on the incssp and rdssp builtins to only have 'nothrow'
llvm-svn: 331560
2018-05-04 21:56:43 +00:00
Craig Topper 934f86a848 [X86] Fix some inconsistent formatting in the first line of our intrinsics headers.
Some were too long and some were too short.

llvm-svn: 331559
2018-05-04 21:45:25 +00:00
Artem Dergachev 2fd6aa7d56 [analyzer] pr37209: Fix casts of glvalues to references.
Many glvalue expressions aren't of their respective reference type -
they are simply glvalues of their value type.

This was causing problems when we were trying to obtain type of the original
expression while evaluating certain glvalue bit-casts.

Fixed by artificially forging a reference type to provide to the casting
procedure.

Differential Revision: https://reviews.llvm.org/D46224

llvm-svn: 331558
2018-05-04 21:39:25 +00:00
Philip Reames 5b39acd111 [LICM] Compute a must execute property for the prefix of the header as we go
Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching.

This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile.

llvm-svn: 331557
2018-05-04 21:35:00 +00:00
Artem Dergachev a2e053638b [analyzer] Treat more const variables and fields as known contants.
When loading from a variable or a field that is declared as constant,
the analyzer will try to inspect its initializer and constant-fold it.
Upon success, the analyzer would skip normal load and return the respective
constant.

The new behavior also applies to fields/elements of brace-initialized structures
and arrays.

Patch by Rafael Stahl!

Differential Revision: https://reviews.llvm.org/D45774

llvm-svn: 331556
2018-05-04 20:52:39 +00:00
Simon Atanasyan b6211d9084 [ELF][MIPS] Reorganize isMipsPIC routine. NFC
llvm-svn: 331555
2018-05-04 20:48:53 +00:00
Simon Atanasyan 86a1219d30 [ELF][MIPS] Add STO_MIPS_MICROMIPS flag to symbols point to microMIPS PLT records
llvm-svn: 331554
2018-05-04 20:48:47 +00:00
Konstantin Zhuravlyov 3fc4067ac4 AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features
llvm-svn: 331553
2018-05-04 20:21:31 +00:00
Sterling Augustine 5891064692 Allow modifying the PrintingPolicy for fully qualified names.
Author: mikhail.ramalho@gmail.com
llvm-svn: 331552
2018-05-04 20:12:39 +00:00
Konstantin Zhuravlyov c2c2eb7d01 AMDGPU: Add D16 instructions preserve unused bits feature
- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4

Differential Revision: https://reviews.llvm.org/D46366

llvm-svn: 331551
2018-05-04 20:06:57 +00:00
Guansong Zhang e1c7a46d5b [OpenMP] Use LIBOMPTARGET_DEVICE_RTL_DEBUG env var to control debug messages on the device side
Summary:
Enable the device side debug messages at compile time, use env var to control at runtime.

To achieve this, an environment data block is passed to the device lib when it is loaded.

By default, the message is off, to enable it, a user need to set LIBOMPDEVICE_DEBUG=1.

Reviewers: grokos

Reviewed By: grokos

Subscribers: openmp-commits

Tags: #openmp

Differential Revision: https://reviews.llvm.org/D46210

llvm-svn: 331550
2018-05-04 19:29:28 +00:00
Geoff Berry 8e4958e760 [MachineLICM] Debug intrinsics shouldn't affect hoist decisions
Summary:
When checking if an instruction stores to a given frame index, check
that the instruction can write to memory before looking at the memory
operands list to avoid e.g. DBG_VALUE instructions that reference a
frame index preventing a load from that index from being hoisted.

Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D46284

llvm-svn: 331549
2018-05-04 19:25:09 +00:00
Shoaib Meenai 57fadab1cb [ObjCARC] Account for catchswitch in bitcast insertion
A catchswitch is both a pad and a terminator, meaning it must be the
only non-phi instruction in its basic block. When we're inserting a
bitcast in the incoming basic block for a phi, if that incoming block is
a catchswitch, we should go up the dominator tree to find a valid
insertion point rather than attempting to insert before the catchswitch
(which would result in invalid IR).

Differential Revision: https://reviews.llvm.org/D46412

llvm-svn: 331548
2018-05-04 19:03:11 +00:00
Michael Berg 7acc81b744 Fast Math Flag mapping into SDNode
Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage.

Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar

Reviewed By: spatel

Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng

Differential Revision: https://reviews.llvm.org/D45710

llvm-svn: 331547
2018-05-04 18:48:20 +00:00
Simon Pilgrim 0e51a125ea [X86] Add WriteEMMS scheduler class
Filled in the missing values from Btver2 SoG or Agner

llvm-svn: 331546
2018-05-04 18:16:13 +00:00
Yan Zhang 4f9ead2356 Add support for ObjC property name to be a single acronym.
Summary:
This change will support cases like:

```
@property(assign, nonatomic) int ID;
```

Reviewers: benhamilton, hokein

Reviewed By: benhamilton

Subscribers: klimek, cfe-commits

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D46374

llvm-svn: 331545
2018-05-04 18:14:08 +00:00
Eric Liu bf4c41c7e1 [clang-format] Refactor #include insertion/deletion functionality into a class.
Summary:
The class will be moved into libToolingCore as followup.

The new behaviors in this patch:
- New #include is inserted in the right position in a #include block to
preserver sorted #includes. This is best effort - only works when the
block is already sorted.
- When inserting multiple #includes to the end of a file which doesn't
end with a "\n" character, a "\n" will be prepended to each #include.
This is a special and rare case that was previously handled. This is now
relaxed to avoid complexity as it's rare in practice.

Reviewers: ilya-biryukov

Reviewed By: ilya-biryukov

Subscribers: klimek, cfe-commits, djasper

Differential Revision: https://reviews.llvm.org/D46180

llvm-svn: 331544
2018-05-04 17:55:13 +00:00
Simon Pilgrim d7ffbc5c7e [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
llvm-svn: 331543
2018-05-04 17:47:46 +00:00
Craig Topper ded8ee07e9 [LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.
We can call the methods in ConstantInt directly. We just need a context.

llvm-svn: 331542
2018-05-04 17:39:08 +00:00
Adhemerval Zanella 6d56294c7f [AArch64] Add missing testcase for r331522
llvm-svn: 331541
2018-05-04 17:21:26 +00:00
Matt Davis 35df8b24af [llvm-mca] Add descriptive names for the TimelineView report characters. NFC.
Summary:
This change makes the TimelineView source simpler to read and easier to modify in the future.
This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb

Subscribers: tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46409

llvm-svn: 331540
2018-05-04 17:19:40 +00:00
Julie Hockett b59cd77c87 [clang-doc] Attaching a name to reference data
This adds the name of the referenced decl, in addition to its USR, to
the saved data, so that the backend can look at an info in isolation and
still be able to construct a human-readable name for it.

Differential Revision: https://reviews.llvm.org/D46281

llvm-svn: 331539
2018-05-04 17:02:13 +00:00
Peter Collingbourne e5ad31d376 Object: The default alignment of a section without alignment flags is 16.
Differential Revision: https://reviews.llvm.org/D46420

llvm-svn: 331538
2018-05-04 16:45:57 +00:00
Peter Collingbourne 9096413f9f obj2yaml: Correctly round-trip default alignment.
Previously we were emitting the "cooked" alignment, which made it hard
to distinguish between that and the default alignment.

Differential Revision: https://reviews.llvm.org/D46418

llvm-svn: 331537
2018-05-04 16:28:41 +00:00
Erich Keane 8668503c8f [NFC]Convert Class to use member initialization instead of inline.
llvm-svn: 331536
2018-05-04 16:19:53 +00:00
Adrian Prantl 3edc63a579 DwarfCompileUnit: Fix another assertion failure on malformed input
that is not rejected by the Verifier.

Thanks to Björn Pettersson for providing a reproducer!

llvm-svn: 331535
2018-05-04 16:10:43 +00:00
Zaara Syeda edc7a8c1e5 [PPC64] Remove support for ELF V1 ABI in LLD - buildbot fix
Fix buildbot error, failure to build with msvc due to error C2446
Use switch instead of ternary operator.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331534
2018-05-04 16:04:04 +00:00
Erich Keane 425f48d480 [clang-cl] Print /showIncludes to stderr, if used in combination with /E, /EP or /P
This replicates 'cl.exe' behavior and allows for both preprocessor output and
dependency information to be extraced with a single compiler invocation.

This is especially useful for compiler caching with tools like Mozilla's sccache.

See: https://github.com/mozilla/sccache/issues/246

Patch By: fxb

Differential Revision: https://reviews.llvm.org/D46394

llvm-svn: 331533
2018-05-04 15:58:31 +00:00
Clement Courbet b18c34bc29 [llvm-exegesis] Fix pfm counter names for BDW.
Summary: They are not consistent with other microarchitectures.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D46434

llvm-svn: 331532
2018-05-04 15:26:12 +00:00
Simon Pilgrim 67cc246dca [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.

llvm-svn: 331531
2018-05-04 15:20:18 +00:00
David Bolvansky 12e42f0f81 [bindings/go] Add Go bindings for volatile loads/stores
Reviewers: whitequark

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46235

llvm-svn: 331530
2018-05-04 15:14:00 +00:00
Zaara Syeda f61b0733a8 [PPC64] Remove support for ELF V1 ABI in LLD
The current support for V1 ABI in LLD is incomplete.
This patch removes V1 ABI support and changes the default behavior to V2 ABI,
issuing an error when using the V1 ABI. It also updates the testcases to V2
and removes any V1 specific tests.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331529
2018-05-04 15:09:49 +00:00
Krzysztof Parzyszek 5291562acd [Hexagon] Remove leftover debugging code after r331527
llvm-svn: 331528
2018-05-04 15:07:30 +00:00
Krzysztof Parzyszek effcc2fb79 [Hexagon] Handle non-immediate constants in HexagonSplitDouble
llvm-svn: 331527
2018-05-04 15:04:48 +00:00
Simon Dardis 65b0492f0d [mips] Correct the predicates of sign extension instructions
And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117

llvm-svn: 331526
2018-05-04 15:00:54 +00:00
Simon Pilgrim bf4c8c0ff2 [X86] Add WriteVecMOVMSKY scheduler class
llvm-svn: 331525
2018-05-04 14:54:33 +00:00
David Major af79e30ad5 Comment fix.
Test commit!

llvm-svn: 331523
2018-05-04 14:41:49 +00:00
Adhemerval Zanella a57ef17ab6 [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32
This patch adds a custom lowering for ISD::MULH{S,U} used on divide by
constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV).

New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL
can be correctly lowered to smull2 and umull2.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46009

llvm-svn: 331522
2018-05-04 14:33:55 +00:00
Peter Smith 2689d9f4f0 [ELF][AArch64] Add aarch64_elf64_le_vec emulation
Android AOSP has started specifying -m aarch64_elf64_le_vec as supported
by gold and BFD. This is a simple change to add the emulation so that LLD
doesn't immediately error when used as a linker in an AOSP build.

Differential Revision: https://reviews.llvm.org/D46429

llvm-svn: 331521
2018-05-04 14:28:29 +00:00
Alexander Kornienko a61d4c959a Remove explicit cfg-temporary-dtors=true
Summary:
Remove explicit -analyzer-config cfg-temporary-dtors=true in analyzer tests,
since this option defaults to true since r326461.

Reviewers: NoQ

Reviewed By: NoQ

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D46393

llvm-svn: 331520
2018-05-04 14:13:14 +00:00
Brian Gesiak ea9144e818 [Coroutines] Catch exceptions in await_resume
Summary:
http://wg21.link/P0664r2 section "Evolution/Core Issues 24" describes a
proposed change to Coroutines TS that would have any exceptions thrown
after the initial suspend point of a coroutine be caught by the handler
specified by the promise type's 'unhandled_exception' member function.
This commit provides a sample implementation of the specified behavior.

Test Plan: `check-clang`

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: cfe-commits, lewissbaker, eric_niebler

Differential Revision: https://reviews.llvm.org/D45860

llvm-svn: 331519
2018-05-04 14:02:37 +00:00
Krzysztof Parzyszek af73d2bdd9 [Hexagon] Skip reserved physical registers when updating liveness
llvm-svn: 331518
2018-05-04 13:59:05 +00:00
Andrea Di Biagio 24fb4fcb93 [llvm-mca] use colors for warnings and notes generated by InstrBuilder.
llvm-svn: 331517
2018-05-04 13:52:12 +00:00
Andrea Di Biagio 49c8591397 [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.
We don't need to pass the instruction index to the method that constructs new
instruction descriptors.

No functional change intended.

llvm-svn: 331516
2018-05-04 13:10:10 +00:00
Simon Pilgrim be51b20127 [X86] Add SchedWriteFRnd fp rounding scheduler classes
Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.

Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.

llvm-svn: 331515
2018-05-04 12:59:24 +00:00
Jeremy Morse 07e8daa66b [X86] Add test case for PR30290s failing behaviour
Following the advice in review D45022, this currently tests for the broken llc
output where an instruction is mis-scheduled. This test is committed in advance
to improve the eventual fixing patch in D45022, making the bad behaviour that
that patch fixes clearer.

llvm-svn: 331514
2018-05-04 10:05:10 +00:00
Peter Smith 9c116180a4 [ELF][AArch64] Add REQUIRES aarch64 to test [NFC]
Forgot to add REQUIRES aarch64 to the test I recently added for D46255.

llvm-svn: 331513
2018-05-04 09:10:18 +00:00
Jeremy Morse 71f17bf855 Word wrap a test-file comment to 80 columns
This is a test commit to check whether my account works.

llvm-svn: 331512
2018-05-04 08:58:06 +00:00