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79466 Commits

Author SHA1 Message Date
Benjamin Kramer 116e99a469 Silence warnings about mixing enums. 
llvm-svn: 148495
 2012-01-19 21:11:13 +00:00
Owen Anderson 4b53e188c1 Add a dump() implementation for sub-instruction MCOperands. 
llvm-svn: 148493
 2012-01-19 19:32:20 +00:00
Owen Anderson c67903cc19 Add a new form of MCOperand, for representing sub-instructions. This is intended for supporting bundles through the MC layer, rather than lowering them pre-MC as we currently do for Thumb2 IT blocks. Since these sub-instruction operands hold pointers to the sub-instructions, it is the responsibility of the target's AsmPrinter to provide storage for them for the duration of the EmitInstruction() call. 
llvm-svn: 148492
 2012-01-19 19:24:37 +00:00
Dan Gohman 8ee108bf98 Set the "tail" flag on pattern-matched objc_storeStrong calls. 
rdar://10531041.

llvm-svn: 148490
 2012-01-19 19:14:36 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Nick Lewycky 219e6bcb71 Actually, this code handles wrapped sets just fine. Noticed by inspection. 
llvm-svn: 148487
 2012-01-19 18:19:42 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Evgeniy Stepanov 4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. 
llvm-svn: 148473
 2012-01-19 12:53:06 +00:00
Craig Topper a875b7ccc7 Folding table additions and fixes for AVX. 
llvm-svn: 148467
 2012-01-19 08:50:38 +00:00
Craig Topper 80576e8d1f Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. 
llvm-svn: 148466
 2012-01-19 08:19:12 +00:00
Evan Cheng c2679b2958 More bundle related API additions. 
llvm-svn: 148465
 2012-01-19 07:47:03 +00:00
Evan Cheng d42aba53e6 Rewriter should definitly rewrite instructions inside bundles. 
llvm-svn: 148464
 2012-01-19 07:46:36 +00:00
Chris Lattner 719f6a9947 Introduce a new MutableArrayRef class, which refers to a series of mutable 
T's that are consequtively in memory.

llvm-svn: 148463
 2012-01-19 06:34:52 +00:00
Evan Cheng 6ca2272183 Enhance finalizeBundle to return end of bundle iterator because it makes sense. 
llvm-svn: 148462
 2012-01-19 06:13:10 +00:00
Jim Grosbach 235c8d2d94 ARM assembly diagnostic caret in better position for FPImm. 
llvm-svn: 148459
 2012-01-19 02:47:30 +00:00
Jim Grosbach 44e5c39c29 Thumb2 relaxation for tADR to t2ADR. 
llvm-svn: 148456
 2012-01-19 02:09:38 +00:00
Jim Grosbach b008df40d3 Add comment and fix range check in condition. 
llvm-svn: 148455
 2012-01-19 01:50:30 +00:00
Jim Grosbach 29ecaa944d Add testcase. 
llvm-svn: 148454
 2012-01-19 01:36:59 +00:00
Lang Hames 966dc0a8f9 Added methods to get the live range immediately before a given slot. Intended to parallel the getVNInfoBefore method. 
llvm-svn: 148453
 2012-01-19 01:36:06 +00:00
Nick Lewycky 9e2c7f659e Space after punctuation. 
llvm-svn: 148451
 2012-01-19 01:13:47 +00:00
Evan Cheng 2879467d4e - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing 
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444
 2012-01-19 00:46:06 +00:00
Nick Lewycky ecc0084f72 Add a TargetOption for disabling tail calls. 
llvm-svn: 148442
 2012-01-19 00:34:10 +00:00
Evan Cheng 1eb2bb2295 Rename Finalizebundle to finalizeBundle to conform to coding guideline. 
llvm-svn: 148440
 2012-01-19 00:06:10 +00:00
Jakob Stoklund Olesen ff482f733b Add experimental -x86-use-regmask command line option. 
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438
 2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen f1fb1d2375 Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
 2012-01-18 23:52:19 +00:00
Jakob Stoklund Olesen 9349351d72 Add a RegisterMaskSDNode class. 
This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.

LowerCall() will attach a register mask that depends on the calling
convention.

llvm-svn: 148436
 2012-01-18 23:52:12 +00:00
Rafael Espindola f5e78fa8d1 Add support for the gnueabihf environment. Patch by Sylvestre Ledru. 
llvm-svn: 148434
 2012-01-18 23:35:29 +00:00
Jim Grosbach 94298a906a Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Jim Grosbach cbd3f27354 Replace FIXME with explanatory comment. 
llvm-svn: 148427
 2012-01-18 22:04:42 +00:00
Jim Grosbach cb80eb2e75 Thumb2 relaxation for LDR(literal). 
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424
 2012-01-18 21:54:16 +00:00
Jim Grosbach d4dbd09d85 MCAssembler tweak for determining when a symbol difference is resolved. 
If the two fragments are in the same Atom, then the difference
expression is resolvable at compile time. Previously we were checking
that they were in the same fragment, but that breaks down in the
presence of instruction relaxation which has multiple fragments in the
same atom.

rdar://10711829

llvm-svn: 148423
 2012-01-18 21:54:12 +00:00
Jim Grosbach 9ab3d8be4e Rename pattern for clarity. 
llvm-svn: 148422
 2012-01-18 21:54:09 +00:00
Dan Gohman 8f12faeb14 Add a depth limit to avoid runaway recursion. 
llvm-svn: 148419
 2012-01-18 21:24:45 +00:00
Dan Gohman 82041c2e60 Use llvm.global_ctors to locate global constructors instead 
of recognizing them by name.

llvm-svn: 148416
 2012-01-18 21:19:38 +00:00
Jakub Staszak 632a355a01 Remove trailing spaces and unneeded includes. 
llvm-svn: 148415
 2012-01-18 21:16:33 +00:00
Nadav Rotem c3cc110bb4 Document the fact that the selection dag changes the vselect condition type 
llvm-svn: 148411
 2012-01-18 20:50:30 +00:00
Lang Hames 1997de0100 Fixed macro condition. 
llvm-svn: 148408
 2012-01-18 19:48:31 +00:00
Jim Grosbach e2d298168c Tidy up. 80 columns. 
llvm-svn: 148401
 2012-01-18 18:52:20 +00:00
Jim Grosbach aba3de99c0 Tidy up. MCAsmBackend naming conventions. 
llvm-svn: 148400
 2012-01-18 18:52:16 +00:00
Bill Wendling 75afc7afe8 Remove dead code. 
llvm-svn: 148384
 2012-01-18 10:10:28 +00:00
Nadav Rotem 3b8f0cc9fa Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted. 
llvm-svn: 148383
 2012-01-18 08:33:18 +00:00
Pete Cooper c52eeed310 Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE 
llvm-svn: 148377
 2012-01-18 04:16:16 +00:00
Jim Grosbach adcc938c46 Thumb2 load/store fixups don't set the thumb bit. 
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.

rdar://10348687.

llvm-svn: 148366
 2012-01-18 00:40:25 +00:00
Jim Grosbach 3b50c9ec7f Move some ARM specific MCAssmebler bits into the ARMAsmBackend. 
llvm-svn: 148364
 2012-01-18 00:23:57 +00:00
Jakob Stoklund Olesen f43b599550 Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
 2012-01-18 00:16:39 +00:00
Daniel Dunbar 9619961e1b [lit] Add a --filter option which is useful when dealing with virtual test 
paths.

llvm-svn: 148362
 2012-01-18 00:03:12 +00:00
Jakub Staszak 62e5f55874 Remove unneeded include. 
llvm-svn: 148360
 2012-01-17 23:53:08 +00:00
Jakob Stoklund Olesen fdbb12b235 Implement ARMBaseRegisterInfo::getCallPreservedMask(). 
Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357
 2012-01-17 23:09:00 +00:00