ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
3563f8cd41
[asan] call __asan_init from .preinit_array. This simplifies __asan_init vs malloc chicken-and-egg situation on Android and probably on other flavours of Linux. Patch by eugenis@google.com.
...
llvm-svn: 146284
2011-12-09 22:09:32 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
...
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
f5b32e52db
SplitBlockPredecessors uses ArrayRef instead of Data and Size.
...
llvm-svn: 146277
2011-12-09 21:19:53 +00:00
dd998ff4df
[fast-isel] Add support for selecting insertvalue.
...
rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
...
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
f85723626c
User a helper overload for a common pattern.
...
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
8a4009dab2
Tidy up. Better base class factoring.
...
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
...
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
5f5fa12413
Tweak debugging output.
...
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
...
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
863683c590
This is now implemented.
...
llvm-svn: 146258
2011-12-09 15:45:57 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
2dc5dec41d
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
...
llvm-svn: 146256
2011-12-09 15:43:55 +00:00
feb9f27de1
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
...
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
...
llvm-svn: 146246
2011-12-09 06:32:46 +00:00
d04d152998
Add -unroll-runtime for unrolling loops with run-time trip counts.
...
Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
llvm-svn: 146245
2011-12-09 06:19:40 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
...
symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
706574a994
Fix comment.
...
llvm-svn: 146226
2011-12-09 01:25:04 +00:00
2f9a0e1b86
Update stale comment.
...
llvm-svn: 146220
2011-12-09 01:18:48 +00:00
053a724483
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
...
llvm-svn: 146219
2011-12-09 01:16:26 +00:00
202cf2f6fc
Revert r146184. I am seeing performance regression cause by this patch in one test case.
...
llvm-svn: 146205
2011-12-08 23:52:00 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
...
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
0a7625d661
Support/FileSystem: Implement recursive_directory_iterator and make
...
directory_iterator preserve InputIterator semantics on copy.
llvm-svn: 146200
2011-12-08 22:50:09 +00:00
fe970725cc
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
...
trivially infinite.
llvm-svn: 146197
2011-12-08 22:36:35 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
...
llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
bb15fec2b8
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
...
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
b94c9a47e9
Refactor. No intentional functionality change.
...
llvm-svn: 146187
2011-12-08 21:48:01 +00:00
0464869922
Add rather verbose stats for fast-isel failures.
...
llvm-svn: 146186
2011-12-08 21:37:10 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
...
For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
1a3c1697f9
Filter "sink to" candidate blocks sooner. This avoids unnecessary computation to determine whether the block dominates all uses or not.
...
llvm-svn: 146184
2011-12-08 21:33:23 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
...
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
...
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
57a7f41d5d
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
...
Fixes failures caused by r146171.
llvm-svn: 146180
2011-12-08 20:51:38 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
4edc7360c7
ARM assembler support for register name aliases.
...
rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
cdf89fdeaf
Make MachineInstr instruction property queries more flexible. This change all
...
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.
llvm-svn: 146168
2011-12-08 19:23:10 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
...
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
...
llvm-svn: 146151
2011-12-08 14:43:19 +00:00
26edb291ac
Fix a bug in the integer-promotion of bitcast operations on vector types.
...
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
llvm-svn: 146150
2011-12-08 13:10:01 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
528ff4bee0
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
...
llvm-svn: 146137
2011-12-08 04:36:44 +00:00
a48e753103
Reverting r145899 as it breaks clang self-hosting
...
llvm-svn: 146136
2011-12-08 03:24:10 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
14e024dff7
Drop the HasInlineAsm flag.
...
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
llvm-svn: 146124
2011-12-08 01:22:39 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
bd97f5d753
Simplify offset verification.
...
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
0dd1bc9c79
Fix copy/past-o.
...
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
...
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
2a82333f54
Don't include alignment padding in BBInfo.Size.
...
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
llvm-svn: 146118
2011-12-08 00:55:02 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
9646c0d046
Fix 80-column.
...
Simplify code.
llvm-svn: 146112
2011-12-08 00:38:45 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
a966c31937
Fix comments.
...
llvm-svn: 146109
2011-12-08 00:11:31 +00:00
dff247868a
EngineBuilder: support for custom TargetOptions. Fixes the
...
ExceptionDemo example.
llvm-svn: 146108
2011-12-07 23:58:57 +00:00
42ee1522b6
Fix comments.
...
llvm-svn: 146107
2011-12-07 23:57:55 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
16be674ec3
Flesh out a bit more of the bitcode use-list ordering preservation code.
...
Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.
llvm-svn: 146090
2011-12-07 22:49:05 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
...
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
d5c173fad0
Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling.
...
llvm-svn: 146087
2011-12-07 22:24:28 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
0bdc083e21
Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate.
...
llvm-svn: 146083
2011-12-07 22:06:02 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
ca2567b861
Begin adding experimental support for preserving use-list ordering of bitcode
...
files. First, add a new block USELIST_BLOCK to the bitcode format. This is
where USELIST_CODE_ENTRYs will be stored. The format of the USELIST_CODE_ENTRYs
have not yet been defined. Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.
llvm-svn: 146078
2011-12-07 21:44:12 +00:00
d63851eb93
These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
...
that he isn't using these any more, so just delete them.
llvm-svn: 146076
2011-12-07 21:35:59 +00:00
78037a900e
ValueEnumerator - debug dump().
...
llvm-svn: 146070
2011-12-07 20:44:46 +00:00
4f864b78e6
Fix comment.
...
llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
...
llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d633c2f120
Nuke inadvertant debugging commit.
...
llvm-svn: 146057
2011-12-07 19:56:16 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
...
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
190c712f73
Remove unneeded semicolon.
...
Skip two looking up at BlockChain.
llvm-svn: 146053
2011-12-07 19:46:10 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
...
rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
8fa0b6927d
Remove unused include.
...
llvm-svn: 146037
2011-12-07 17:18:31 +00:00
1d578e8835
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
...
llvm-svn: 146031
2011-12-07 08:30:53 +00:00
302cf8d5d0
Adjust the stack by one pointer size for all frameless stacks.
...
llvm-svn: 146030
2011-12-07 07:58:55 +00:00
3c86459997
Fix off-by-one error when encoding the stack size for a frameless stack.
...
llvm-svn: 146029
2011-12-07 07:49:49 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
421caa4278
Adding missing anchor to DATDeltaAlgorithm.
...
llvm-svn: 146025
2011-12-07 06:44:23 +00:00
ac9df3d411
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
...
llvm-svn: 146024
2011-12-07 06:34:06 +00:00
16c744180d
make base register selection used in eliminateFrameIndex 64-bit clean
...
llvm-svn: 146023
2011-12-07 06:34:02 +00:00
abbc2529c1
set mayStore and mayLoad on CR pseudos
...
llvm-svn: 146022
2011-12-07 06:33:57 +00:00
2ba61e47a9
64-bit LR8 load should use X11 not R11
...
llvm-svn: 146021
2011-12-07 06:32:37 +00:00
2f0400b780
Eliminate delta argument from AdjustBBOffsetsAfter.
...
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
llvm-svn: 146018
2011-12-07 05:17:30 +00:00
97c857199e
Compute some alignment information for each basic block.
...
These fields are not used for anything yet.
llvm-svn: 146017
2011-12-07 04:17:35 +00:00
f9081a8afe
Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target.
...
llvm-svn: 146015
2011-12-07 03:55:52 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
...
The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
af748e1180
Move common expression into a method.
...
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
585ce30b8b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
...
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
e2b3ff2a07
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
...
No functional change is intended.
llvm-svn: 146005
2011-12-07 01:08:25 +00:00
6ad6848522
Add missing check.
...
llvm-svn: 146004
2011-12-07 01:08:22 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
...
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
ed8b3e38ec
Support vector bitcasts in the AsmPrinter. PR11495.
...
llvm-svn: 146001
2011-12-07 00:50:54 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
b0d91abec0
Add MachineOperand IsInternalRead flag.
...
This flag is used when bundling machine instructions. It indicates
whether the operand reads a value defined inside or outside its bundle.
llvm-svn: 145997
2011-12-07 00:22:07 +00:00
0e58cba286
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
...
llvm-svn: 145996
2011-12-07 00:11:56 +00:00
c007ab8551
Remove unneeded type.
...
llvm-svn: 145995
2011-12-07 00:08:00 +00:00
47c24c2084
ARM: Parameterize the immediate operand type for NEON VSHLL.
...
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
llvm-svn: 145994
2011-12-07 00:02:17 +00:00
d4d2b05eba
- Remove unneeded #includes.
...
- Remove unused types/fields.
- Add some constantness.
llvm-svn: 145993
2011-12-06 23:59:33 +00:00
cc6bfa8e79
Revert r145971: "Use conservative size estimate for tBR_JTr."
...
This caused more offset errors.
llvm-svn: 145980
2011-12-06 22:41:31 +00:00
efdd2f8fef
Re-enable compact unwind. It seems to work now. <rdar://problem/10441838>
...
llvm-svn: 145977
2011-12-06 22:18:12 +00:00
67a70c995a
Explicitly check for the different SUB instructions.
...
llvm-svn: 145976
2011-12-06 22:14:27 +00:00
2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
33fe130e12
Use conservative size estimate for tBR_JTr.
...
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
llvm-svn: 145971
2011-12-06 21:55:39 +00:00
2fa7448f31
Remove alignment from deserted constant islands.
...
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
llvm-svn: 145970
2011-12-06 21:55:35 +00:00
5a173cd367
Encode the total stack if there isn't a frame.
...
llvm-svn: 145969
2011-12-06 21:34:01 +00:00
a73c0c99ea
* Add a macro to remove a magic number.
...
* Rename variables to reflect what they're actually used for.
llvm-svn: 145968
2011-12-06 21:23:42 +00:00
2a2b37ea4a
Pretty-print basic block alignment.
...
llvm-svn: 145965
2011-12-06 21:08:39 +00:00
bde7f8ffe2
add RESTORE_CR and support CR unspills
...
llvm-svn: 145961
2011-12-06 20:55:36 +00:00
4ec02b02ac
remove old FIXME
...
llvm-svn: 145960
2011-12-06 20:52:56 +00:00
87571b6392
Check the correct value for small stack sizes. Also modify some comments.
...
llvm-svn: 145954
2011-12-06 19:16:17 +00:00
a4e87944a8
For a small sized stack, we encode that value directly with no "stack adjust" value.
...
llvm-svn: 145952
2011-12-06 19:09:06 +00:00
04424665c3
PTX: Continue to fix up the register mess.
...
llvm-svn: 145947
2011-12-06 17:39:48 +00:00
3063ac87aa
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
...
llvm-svn: 145946
2011-12-06 17:39:46 +00:00
ac35a4d0f7
use space star instead of star space
...
llvm-svn: 145944
2011-12-06 17:34:16 +00:00
9aa6137d97
add missing point at the end of sentences
...
llvm-svn: 145943
2011-12-06 17:34:11 +00:00
b5188f163a
Simplify common predecessor finding.
...
- Walking over pred_begin/pred_end is an expensive operation.
- PHINodes contain a value for each predecessor anyway.
- While it may look like we used to save a few iterations with the set,
be aware that getIncomingValueForBlock does a linear search on
the values of the phi node.
- Another -5% on ARMDisassembler.cpp (Release build). This was the last
entry in the profile that was obviously wasting time.
llvm-svn: 145937
2011-12-06 16:14:29 +00:00
b3bd019cd7
Push StringRefs through the metadata interface.
...
llvm-svn: 145934
2011-12-06 11:50:26 +00:00
83320e03e6
Add X86ISD::HADD/HSUB to getTargetNodeName
...
llvm-svn: 145929
2011-12-06 09:31:36 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
...
llvm-svn: 145927
2011-12-06 09:04:59 +00:00
8d4ba198d6
Merge floating point and integer UNPCK X86ISD node types.
...
llvm-svn: 145926
2011-12-06 08:21:25 +00:00
3cb802c775
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
...
llvm-svn: 145924
2011-12-06 05:31:16 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
...
llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
87cfffe149
Explicit symbols for gnu mimicing relocations. Patch by Jack Carter
...
llvm-svn: 145911
2011-12-06 03:34:42 +00:00
1b1a122b4c
Add register HWR29 numbering. Patch by Jack Carter
...
llvm-svn: 145910
2011-12-06 03:34:36 +00:00
5df9096584
LSR: prune undesirable formulae early.
...
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
llvm-svn: 145906
2011-12-06 03:13:31 +00:00
c1610bede1
Mix some minor misuse of MachineBasicBlock iterator.
...
llvm-svn: 145903
2011-12-06 02:49:06 +00:00
d2971264c6
Removed isWinToJoinCrossClass from the register coalescer.
...
The new register allocator is much more able to split back up ranges too constrained by register classes.
Fixes <rdar://problem/10466609>
llvm-svn: 145899
2011-12-06 02:06:50 +00:00
52f24d7a32
Kill off the LoopSplitter. It's not being used or maintained.
...
llvm-svn: 145897
2011-12-06 01:57:59 +00:00
4e87e850a2
Add a comment.
...
llvm-svn: 145896
2011-12-06 01:57:48 +00:00
425e180ce8
Tidy up value checking.
...
llvm-svn: 145895
2011-12-06 01:53:17 +00:00
d3002490bf
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
...
llvm-svn: 145894
2011-12-06 01:48:32 +00:00
b13b6a04d0
Update PBQP's analysis usage to reflect the requirements of the inline spiller.
...
llvm-svn: 145893
2011-12-06 01:45:57 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
10e1252269
Use logarithmic units for basic block alignment.
...
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
llvm-svn: 145889
2011-12-06 01:26:19 +00:00
f7cef7ecad
The compact encoding of the registers are 3-bits each. Make sure we shift the
...
value over that much.
llvm-svn: 145888
2011-12-06 01:26:14 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
2608157f79
Use an existing function.
...
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
25b63fa117
Move target-specific logic out of generic MCAssembler.
...
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
2011-12-06 00:47:03 +00:00
72d4d32cd6
Expose a switch for the new gcov format.
...
llvm-svn: 145880
2011-12-06 00:29:13 +00:00
8abf65a130
Probably not a good idea to convert a single vector load into a memcpy. We
...
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
llvm-svn: 145879
2011-12-06 00:19:08 +00:00
46be301c4c
Tidy up. Hard tabs.
...
llvm-svn: 145878
2011-12-06 00:13:09 +00:00
18e2fe47fa
Switch MCAssembler to method names starting w/ lower-case.
...
per http://llvm.org/docs/CodingStandards.html#ll_naming
llvm-svn: 145873
2011-12-06 00:03:48 +00:00
34a7c6dfd7
Simple branch relaxation for Thumb2 Bcc instructions.
...
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
llvm-svn: 145871
2011-12-05 23:45:46 +00:00
897a57ecda
Silence tsan false-positives (tsan can't track things which are only safe due to
...
memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.
llvm-svn: 145869
2011-12-05 23:07:05 +00:00
3277557741
Update comment.
...
llvm-svn: 145866
2011-12-05 22:53:09 +00:00
19446a07a7
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
...
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
llvm-svn: 145865
2011-12-05 22:37:00 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
...
rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
...
llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
...
llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
...
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
...
llvm-svn: 145819
2011-12-05 17:55:17 +00:00
72a26e8b8d
don't include CR bit subregs in callee-saved list
...
llvm-svn: 145818
2011-12-05 17:55:12 +00:00
b544019a60
add register pressure for CR regs
...
llvm-svn: 145816
2011-12-05 17:54:17 +00:00
13231037f0
Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks.
...
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.
llvm-svn: 145810
2011-12-05 17:23:27 +00:00
51bec1a37a
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
...
llvm-svn: 145804
2011-12-05 07:27:14 +00:00
6a55b1dd9f
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
...
llvm-svn: 145803
2011-12-05 06:56:46 +00:00
3924cb0267
Add support for vectors of pointers.
...
llvm-svn: 145801
2011-12-05 06:29:09 +00:00
8dda5d0f06
Add inline subprogram names to the name lookup table since they may
...
not get there any other way.
llvm-svn: 145789
2011-12-04 06:02:38 +00:00
80381f6cbf
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
...
AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
71ba18c1e0
Simplify code. No functionality change.
...
-3% on ARMDissasembler.cpp.
llvm-svn: 145773
2011-12-03 16:18:22 +00:00
bbf3c60786
Clear the new cache.
...
llvm-svn: 145771
2011-12-03 15:19:55 +00:00
3664708378
Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps.
...
-15% on ARMDisassembler.cpp (Release build). It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.
llvm-svn: 145770
2011-12-03 15:16:45 +00:00
006e43bcc0
Check for stack space more intelligently.
...
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
...
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
8fd1254a0a
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
...
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
llvm-svn: 145745
2011-12-03 02:45:50 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
e03fe83d98
Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur
...
Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
llvm-svn: 145731
2011-12-03 00:04:30 +00:00
0155a63513
Add support for constant folding the pow intrinsic.
...
rdar://10514247
llvm-svn: 145730
2011-12-03 00:00:03 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
...
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
81c9003695
ARM encoder method needs the physical register number, not the enum.
...
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
4d2b871cda
Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller.
...
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.
llvm-svn: 145690
2011-12-02 18:37:31 +00:00
bccc4c17f3
Check for error after InstantiateMultclassDef.
...
llvm-svn: 145689
2011-12-02 18:33:03 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
b67440367f
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
...
llvm-svn: 145681
2011-12-02 08:18:41 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
...
llvm-svn: 145680
2011-12-02 07:16:01 +00:00
f9ce7b60ef
remove unneeded FIXME comment
...
llvm-svn: 145679
2011-12-02 04:58:17 +00:00
4201820275
make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop
...
llvm-svn: 145677
2011-12-02 04:58:07 +00:00
58ca360081
update PPC 940 hazard rec. to function in postRA mode
...
llvm-svn: 145676
2011-12-02 04:58:02 +00:00
43a33066b4
Fix a few more places where TargetData/TargetLibraryInfo is not being passed.
...
Add FIXMEs to places that are non-trivial to fix.
llvm-svn: 145661
2011-12-02 01:26:24 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
576c0f8e54
Abuse of mass replace isn't warranted even when the build is failing. Thanks
...
for the suggestion, Eric.
llvm-svn: 145643
2011-12-01 23:16:03 +00:00
54a506dcb1
Fix build by not assuming TLI is guaranteed. Will have to track down cases where
...
TLI isn't being passed to ensure we don't miss opportunities to fold calls.
llvm-svn: 145641
2011-12-01 22:38:31 +00:00
3367123b12
Prevent library calls from being folded if -fno-builtin has been specified.
...
rdar://10500969
llvm-svn: 145639
2011-12-01 22:14:50 +00:00
c19f0b7357
CodeGen: fix CMake build
...
Missing file from r145629.
llvm-svn: 145634
2011-12-01 21:49:23 +00:00
19a58df9bb
ExecutionEngine: honor optimization level
...
It was getting ignored after r144788.
Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.
llvm-svn: 145633
2011-12-01 21:49:21 +00:00
e6de63dfc5
Last bit of TargetLibraryInfo propagation. Also fixed a case for TargetData
...
where it appeared beneficial to pass.
More of rdar://10500969
llvm-svn: 145630
2011-12-01 21:29:16 +00:00
08ebdc1e71
Add a deterministic finite automaton based packetizer for VLIW architectures
...
llvm-svn: 145629
2011-12-01 21:10:21 +00:00
54c9462c77
Fix unreachable return & simplify some branches.
...
llvm-svn: 145627
2011-12-01 20:58:30 +00:00
f60485c4cf
Dummy commit to check commit access.
...
llvm-svn: 145619
2011-12-01 19:15:08 +00:00
fdddc27143
Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment
...
llvm-svn: 145618
2011-12-01 19:13:26 +00:00
d594bac68b
[asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found
...
llvm-svn: 145611
2011-12-01 18:54:53 +00:00
676c093758
Add missing functions.
...
llvm-svn: 145608
2011-12-01 18:26:19 +00:00
3ced545ccf
Autodetect bulldozers.
...
llvm-svn: 145607
2011-12-01 18:24:17 +00:00
10fe1fe39e
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
...
llvm-svn: 145596
2011-12-01 17:54:37 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
...
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
3a15e14520
Add some missing anchors.
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llvm-svn: 145578
2011-12-01 08:00:17 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
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llvm-svn: 145573
2011-12-01 04:49:21 +00:00
bc5c524b71
Added instcombine pattern to spot comparing -val or val against 0.
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(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"
Fixes <rdar://problem/10482509>
llvm-svn: 145563
2011-12-01 03:58:40 +00:00
c24b86ffbe
Propagate TargetLibraryInfo throughout ConstantFolding.cpp and
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InstructionSimplify.cpp. Other fixups as needed.
Part of rdar://10500969
llvm-svn: 145559
2011-12-01 03:08:23 +00:00
e659b8459e
Make use of "getScalarType()". No functionality change.
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llvm-svn: 145556
2011-12-01 02:39:36 +00:00
c1870b2633
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
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llvm-svn: 145553
2011-12-01 01:43:47 +00:00
dc436f95d2
make asan work at -O0, llvm part. Patch by glider@google.com
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llvm-svn: 145530
2011-11-30 22:19:26 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
6cff9df298
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
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<rdar://problem/10497732>.
llvm-svn: 145523
2011-11-30 21:54:15 +00:00
23c30b90e3
Remove unused variable
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llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
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llvm-svn: 145510
2011-11-30 19:35:44 +00:00
Jim Grosbach