a651a62340
[SKX] Enable lowering of integer CMP operations.
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Added new types to Legalizer.
Fixed getSetCCResultType function
Added lowering tests.
Reviewed by Elena Demikhovsky.
llvm-svn: 216717
2014-08-29 08:46:04 +00:00
7ca7df0bf9
[SKX] Enabling load/store instructions: encoding
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Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214719
2014-08-04 14:35:15 +00:00
0b79be8ab2
AVX-512: optimized icmp -> sext -> icmp pattern
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llvm-svn: 200849
2014-02-05 16:17:36 +00:00
9d56f1e0e5
AVX512: combining setcc and zext is wrong on AVX512
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because vector compare instruction puts result in mask register.
llvm-svn: 199798
2014-01-22 12:26:19 +00:00
c5f6726a24
AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader).
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Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.
llvm-svn: 197482
2013-12-17 08:33:15 +00:00
53d0b492f5
[X86] Perform VSELECT DAG combines also before DAG type legalization.
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If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.
This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.
Reviewer: Nadav
llvm-svn: 190105
2013-09-05 23:02:56 +00:00
1490c5eb5b
AVX-512: added arithmetic and logical operations.
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ADD, SUB, MUL integer and FP types. OR, AND, XOR.
Added embeded broadcast form for these instructions.
llvm-svn: 188673
2013-08-19 13:26:14 +00:00
60b1f289f2
AVX-512: Added CMP and BLEND instructions.
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Lowering for SETCC.
llvm-svn: 188265
2013-08-13 13:24:07 +00:00
Robert Khasanov