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24770 Commits

Author SHA1 Message Date
Nate Begeman 01364fbba8 Update the PPC compilation callback code to not need weird abi-violating 
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.

llvm-svn: 28049
 2006-05-02 04:50:05 +00:00
Chris Lattner 2d3a02725d Add pass ID's for various passes, so they can be AddRequiredID. Patch by 
Domagoj Babic!

llvm-svn: 28048
 2006-05-02 04:24:36 +00:00
Jeff Cohen 470f431f44 De-virtualize SwitchSection. 
llvm-svn: 28047
 2006-05-02 03:58:45 +00:00
Jeff Cohen f34ddb1e0d De-virtualize EmitZeroes. 
llvm-svn: 28046
 2006-05-02 03:46:13 +00:00
Jeff Cohen bfe9ffb449 Finish support for Microsoft ML/MASM. May still be a few rough edges. 
llvm-svn: 28045
 2006-05-02 03:11:50 +00:00
Jeff Cohen 24a62a9bc1 Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). 
llvm-svn: 28044
 2006-05-02 01:16:28 +00:00
Chris Lattner 4b177f089e Put instruction names into the first non TargetInstrInfo namespace found. 
llvm-svn: 28043
 2006-05-01 23:46:16 +00:00
Chris Lattner 5104e3b833 New testcase that crashes the new CFE. 
llvm-svn: 28042
 2006-05-01 23:18:55 +00:00
Chris Lattner fd0a5478a1 Fix a latent bug that my spiller patch last week exposed: we were leaving 
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.

llvm-svn: 28041
 2006-05-01 22:03:24 +00:00
Chris Lattner ab7dbe0cc9 When promoting a load to a reg-reg copy, where the load was a previous 
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.

llvm-svn: 28040
 2006-05-01 21:17:10 +00:00
Chris Lattner 4dee67c2cd Remove previous patch, which wasn't quite right. 
llvm-svn: 28039
 2006-05-01 21:16:03 +00:00
Chris Lattner 017b93dd7c instructions can be in different namespaces. Make sure to use the right 
one for each instruction.

llvm-svn: 28038
 2006-05-01 17:01:17 +00:00
Chris Lattner 85e9909755 Put PHI/INLINEASM into the correct namespace. 
llvm-svn: 28037
 2006-05-01 17:00:49 +00:00
Evan Cheng 8e63393bc3 Formating 
llvm-svn: 28036
 2006-05-01 09:30:17 +00:00
Evan Cheng 0d084fb9ca Dis-favor stores more 
llvm-svn: 28035
 2006-05-01 09:20:44 +00:00
Evan Cheng 24e795496d Bottom up register-pressure reduction scheduler now pushes store operations 
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.

llvm-svn: 28033
 2006-05-01 09:14:40 +00:00
Evan Cheng c2ef5e34a8 Mark instructions whose pattern is (store ...) isStore. 
llvm-svn: 28032
 2006-05-01 09:04:20 +00:00
Evan Cheng 10ff7b27ce Didn't mean ScheduleDAGList.cpp to make the last checkin. 
llvm-svn: 28030
 2006-05-01 08:56:34 +00:00
Evan Cheng a656242690 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. 
llvm-svn: 28029
 2006-05-01 08:54:57 +00:00
Chris Lattner 78d9ae3f0c Intel mode no longer uses %'s on registers 
llvm-svn: 28028
 2006-05-01 05:56:51 +00:00
Chris Lattner 563f0417d2 Remove %'s from register names when in intel mode. 
llvm-svn: 28027
 2006-05-01 05:53:50 +00:00
Chris Lattner 25f55ae74a Format #APP lines a bit nicer 
llvm-svn: 28026
 2006-05-01 04:11:03 +00:00
Evan Cheng f71f0f2e0b Local spiller kills a store if the folded restore is turned into a copy. 
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.

llvm-svn: 28024
 2006-04-30 08:41:47 +00:00
Jeff Cohen 71c2e0f262 Mingw32 patches supplied by Anton Korobeynikov. 
llvm-svn: 28023
 2006-04-29 18:41:44 +00:00
Chris Lattner 2b48a94413 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c 
with some changes I have to the new CFE.

llvm-svn: 28022
 2006-04-28 23:33:20 +00:00
Evan Cheng d369603df9 I can't spell: Register, not Regsiter. 
llvm-svn: 28021
 2006-04-28 23:19:39 +00:00
Evan Cheng b244b80172 Implemented x86 inline asm b, h, w, k modifiers. 
llvm-svn: 28020
 2006-04-28 23:11:40 +00:00
Chris Lattner 655d08fda8 Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll 
llvm-svn: 28019
 2006-04-28 22:21:41 +00:00
Chris Lattner 00aaa76da3 new testcase miscompiled by instcombine 
llvm-svn: 28018
 2006-04-28 22:17:20 +00:00
Chris Lattner 84b49d51be Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll 
llvm-svn: 28017
 2006-04-28 21:56:10 +00:00
Chris Lattner a2cef87a30 testcase that crashes the ppc backend, which can't sextinreg(i1) 
llvm-svn: 28016
 2006-04-28 21:52:24 +00:00
Evan Cheng 88decded82 Initial caller side support (for CCC only, not FastCC) of 128-bit vector 
passing by value.

llvm-svn: 28015
 2006-04-28 21:29:37 +00:00
Evan Cheng 68a44dc445 Bare-bone X86 inline asm printer support. 
llvm-svn: 28014
 2006-04-28 21:19:05 +00:00
Evan Cheng e3ca069d35 Update. It should use two shufps, not three! 
llvm-svn: 28013
 2006-04-28 18:55:34 +00:00
Evan Cheng c5e8ce8b8c Remove the temporary option: -no-isel-fold-inflight 
llvm-svn: 28012
 2006-04-28 18:54:11 +00:00
Evan Cheng 3cd4362ade Implement four-wide shuffle with 2 shufps if no more than two elements come 
from each vector. e.g.
        shuffle(G1, G2, 7, 1, 5, 2)
==>
        movaps _G2, %xmm0
        shufps $151, _G1, %xmm0
        shufps $216, %xmm0, %xmm0

llvm-svn: 28011
 2006-04-28 07:03:38 +00:00
Chris Lattner 1b7a51520c Fix PR743: emit -help output of a tool to cout, not cerr. 
llvm-svn: 28010
 2006-04-28 05:36:25 +00:00
Evan Cheng d43c5c6046 TargetLowering::LowerArguments should return a VBIT_CONVERT of 
FORMAL_ARGUMENTS SDOperand in the return result vector.

llvm-svn: 28009
 2006-04-28 05:25:15 +00:00
Chris Lattner 79c50d96c9 Mapping of physregs can make it so that the designated and input physregs are 
the same.  In this case, don't emit a noop copy.

llvm-svn: 28008
 2006-04-28 04:43:18 +00:00
Chris Lattner e63d808b6e Fix Transforms/Reassociate/2006-04-27-ReassociateVector.ll 
llvm-svn: 28007
 2006-04-28 04:14:49 +00:00
Chris Lattner 7abfb81e30 new testcase 
llvm-svn: 28006
 2006-04-28 04:14:29 +00:00
Evan Cheng f0157cb0bc Use movaps instead of movapd for spill / restore. 
llvm-svn: 28005
 2006-04-28 02:23:35 +00:00
Evan Cheng 51ab4498e7 Added a temporary option -no-isel-fold-inflight to control whether a "inflight" 
node can be folded.

llvm-svn: 28003
 2006-04-28 02:09:19 +00:00
Evan Cheng 54acf6eddc When isel'ing a node, mark its operands "InFlight" before selecting them. These 
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.

llvm-svn: 28002
 2006-04-28 02:08:10 +00:00
Chris Lattner 84e95d00b5 When we have a two-address instruction where the input cannot be clobbered 
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!

llvm-svn: 28001
 2006-04-28 01:46:50 +00:00
Evan Cheng c4d77c46b8 Test case for PR748 
llvm-svn: 28000
 2006-04-28 01:21:37 +00:00
Chris Lattner a4c2c4a276 Add a note 
llvm-svn: 27999
 2006-04-28 00:04:05 +00:00
Chris Lattner b209131b56 Add a note 
llvm-svn: 27998
 2006-04-27 21:40:57 +00:00
Chris Lattner b6cb64b7e6 Add support for inserting undef into a vector. This implements 
Transforms/InstCombine/vec_insert_to_shuffle.ll

llvm-svn: 27997
 2006-04-27 21:14:21 +00:00
Chris Lattner 51fecaa8b3 This should turn into one vector shuffle instruction. 
llvm-svn: 27996
 2006-04-27 21:13:58 +00:00