9696f63d3e
Now support instructions with implicit write to non-flag registers.
...
llvm-svn: 24878
2005-12-20 07:37:41 +00:00
6af02635a7
Added a hook to print out names of target specific DAG nodes.
...
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
2dd7e06d8e
Added a break that I meant to include originally, for efficiency. Basically
...
it keeps it from trying to add the same node to the node set
over and over if it matches multiple given patterns. Also in cases where there
are a lot of patterns to be matched, and it matches an early one, this
will make the script run slightly faster. It's more there because it logically
should be, than anything else, I mean, Python is never going to be fast ;-)
llvm-svn: 24876
2005-12-20 02:03:23 +00:00
2af3ee4bdd
Fix a nasty latent bug in the legalizer that was triggered by my patch
...
last night, breaking crafty and twolf. Make sure that the newly found
legal nodes are themselves not re-legalized until the next iteration.
Also, since this functionality exists now, we can reduce number of legalizer
iterations by depending on this behavior instead of having to misuse 'do
another iteration' to get the same effect.
llvm-svn: 24875
2005-12-20 00:53:54 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
fe90b604a4
Lefted out a fix in the previous check in.
...
llvm-svn: 24873
2005-12-20 00:06:17 +00:00
c126397a69
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
...
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
llvm-svn: 24872
2005-12-19 23:40:42 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
6fc31046aa
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
9fd9541367
Print out opcode number if it's an unknown target node.
...
llvm-svn: 24869
2005-12-19 23:11:49 +00:00
19b9f15377
Fix another bug related to chain / flag.
...
llvm-svn: 24868
2005-12-19 22:40:04 +00:00
1d9b671de0
It's essential we clear CodeGenMap after isel every basic block!
...
llvm-svn: 24867
2005-12-19 22:36:02 +00:00
50b2d302d5
Fix a case where the DAG Combiner would accidentally CSE flag-producing nodes,
...
creating graphs that cannot be scheduled.
llvm-svn: 24866
2005-12-19 22:21:21 +00:00
7671a5b844
Added the llvm-kernel project to the list of automatically configured
...
projects.
llvm-svn: 24865
2005-12-19 20:27:24 +00:00
757035ead9
Prefix DSA specific options with dsa.
...
Make the dsa-alloc-list and dsa-free-list options hidden.
llvm-svn: 24864
2005-12-19 20:14:38 +00:00
45bb70d8f9
Added an option to specify the names of heap freeing functions.
...
llvm-svn: 24863
2005-12-19 19:54:23 +00:00
aa0fed0148
Added a command line option that allows the user to specify a list of
...
functions that allocate memory.
llvm-svn: 24862
2005-12-19 17:38:39 +00:00
9b9688aeb8
Amend comment.
...
llvm-svn: 24861
2005-12-19 16:32:26 +00:00
ce23987e6b
Create a strong dependency for loads following stores. This will leave a
...
latency period between the two.
llvm-svn: 24860
2005-12-19 16:30:13 +00:00
7767a654b0
Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
...
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
llvm-svn: 24859
2005-12-19 07:57:53 +00:00
9bd85c2f19
Fixes for a number of bugs: save flag results in CodeGenMap, folded chains
...
may not all have ResNo == 0.
llvm-svn: 24858
2005-12-19 07:18:51 +00:00
631c9df853
don't emit 'add %o6, 0, %o6' instructions
...
llvm-svn: 24857
2005-12-19 02:51:12 +00:00
5b9c9f9d36
Fix calls to functions returning i64
...
llvm-svn: 24856
2005-12-19 02:15:51 +00:00
655fac2c95
Correct bool truncstore operand order
...
llvm-svn: 24855
2005-12-19 02:06:50 +00:00
2c792ccc62
add the other bool zextload as well
...
llvm-svn: 24854
2005-12-19 01:44:58 +00:00
766170c6ee
implement zextload bool
...
llvm-svn: 24853
2005-12-19 01:43:04 +00:00
9be456300e
mark some unsupported ops as unsupported
...
llvm-svn: 24852
2005-12-19 01:39:40 +00:00
136f465fa2
This is a script to extract nodes and edges associated with those nodes
...
from a dot file that is the output of DSA. Nodes to extract
are specified by giving the name of the node seen in the graphical
representation, i.e. in the .ps if the node is specified %xyz
asking for just x, xy, or xyz will retain it in the output file.
Because it operates on substrings underspecifying may result
in additional unexpected nodes. Be as specific as possible.
Obviously, however, if you ask for %xyz and there is a
getelementptr of %xyz you will get both nodes. Some manual
editing may still be necessary because of this, but this script
can pare down 10,000 line files to 20 line files, making like easier.
llvm-svn: 24851
2005-12-19 01:23:31 +00:00
e59941810a
Fix syntax for indirect calls. This fixes Olden/mst
...
llvm-svn: 24850
2005-12-19 01:22:53 +00:00
bead785656
Keep stack frames 8-byte aligned. This fixes olden/voronoi
...
llvm-svn: 24849
2005-12-19 01:15:13 +00:00
9078c84654
apparently rdy isn't actually a psuedo instruction. Use rd %y
...
llvm-svn: 24848
2005-12-19 00:53:02 +00:00
d2e885e321
add fneg/fabs support for doubles
...
llvm-svn: 24847
2005-12-19 00:50:12 +00:00
14ee61ef00
Various cleanups to this pass, no functionality change
...
llvm-svn: 24846
2005-12-19 00:46:20 +00:00
d2a07eebcd
add bool truncstores
...
llvm-svn: 24845
2005-12-19 00:19:21 +00:00
15bd5ea92f
Elimiante SP and FP, which weren't members of the IntRegs register class
...
llvm-svn: 24844
2005-12-19 00:06:52 +00:00
c06da626b4
Make sure to relegalize new nodes
...
llvm-svn: 24843
2005-12-18 23:54:29 +00:00
f5f80cb947
The sun assembler only supports .xword in V9 mode.
...
llvm-svn: 24842
2005-12-18 23:36:45 +00:00
1ac15547d6
Configure the asmwriter to allow constant pools to be printed correctly
...
llvm-svn: 24841
2005-12-18 23:35:05 +00:00
030672f16b
add support for integer extloads
...
llvm-svn: 24840
2005-12-18 23:18:37 +00:00
c70ed7721b
Add support for undef
...
llvm-svn: 24839
2005-12-18 23:10:57 +00:00
4c3c3ac218
Add support for calls to external symbols
...
llvm-svn: 24838
2005-12-18 23:07:11 +00:00
388f3043b0
we have no memcpy
...
llvm-svn: 24837
2005-12-18 23:00:27 +00:00
c65cd5a03e
Fix a crash on a call with no arguments
...
llvm-svn: 24836
2005-12-18 22:57:47 +00:00
c7cb351aac
Keep VC++ happy.
...
llvm-svn: 24835
2005-12-18 22:20:05 +00:00
2f5fb6a720
This is handled by the autogen'd code
...
llvm-svn: 24834
2005-12-18 21:06:11 +00:00
f7ae0a95fe
Handle basic block nodes
...
llvm-svn: 24833
2005-12-18 21:05:44 +00:00
1958690ff2
Change return lowering so that we can autogen the matching code.
...
llvm-svn: 24832
2005-12-18 21:03:04 +00:00
1febcd672c
Add an accessor
...
llvm-svn: 24831
2005-12-18 21:00:53 +00:00
02e9904ee5
Implement Calls for V8. This would be completely autogenerated except for
...
a small bug in tblgen. When that is fixed, we can remove the ISD::Call case
in Select.
llvm-svn: 24830
2005-12-18 15:55:15 +00:00
abb11cc83e
More fixes for Selection of copyto/fromreg with a flag
...
llvm-svn: 24829
2005-12-18 15:45:51 +00:00
ebcfa0c210
More corrections for flagged copyto/from reg
...
llvm-svn: 24828
2005-12-18 15:36:21 +00:00
fc3d4f8fd8
Select copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24827
2005-12-18 15:28:25 +00:00
e3c67e97c7
legalize copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24826
2005-12-18 15:27:43 +00:00
a0be18c9a4
Implement the full V8 ABI for incoming arguments.
...
llvm-svn: 24825
2005-12-18 13:33:06 +00:00
8d1db078cb
Push ops list, asm string, and pattern all the way up to InstV8. Move the
...
InstV8 class to the InstrFormats file where it belongs.
llvm-svn: 24824
2005-12-18 08:21:00 +00:00
7cee2c9a5b
Give V8 select_cc, in the spirit of the PPC backend
...
llvm-svn: 24823
2005-12-18 08:13:54 +00:00
9de2958138
remove some unused instructions
...
llvm-svn: 24822
2005-12-18 07:15:17 +00:00
a9f0d108b1
V8 doesn't have FP extload
...
llvm-svn: 24821
2005-12-18 07:13:32 +00:00
d6806875d0
simplifications, fix typo
...
llvm-svn: 24820
2005-12-18 07:09:06 +00:00
c5609aab11
add a node, for completeness
...
llvm-svn: 24819
2005-12-18 07:05:21 +00:00
4492b1b7a0
Add frameindex support
...
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions
llvm-svn: 24818
2005-12-18 06:59:57 +00:00
9dcfe37e76
Tighten up some checks
...
llvm-svn: 24817
2005-12-18 06:40:34 +00:00
c97b7d0be9
Fix a bug Sabre was having where the DAG root was a group. The group dominator
...
needed to be added to the ordering list, not the first member of the group.
llvm-svn: 24816
2005-12-18 04:40:52 +00:00
e220821deb
Groups were not emitted if the dominator node and the node in the ordering list
...
were not the same node. Ultimately the test was bogus.
llvm-svn: 24815
2005-12-18 03:59:21 +00:00
53c1f75090
Since extload can also be used by FP, split STDIntExtLoad into two parts,
...
one for use with extload, one for use with sextload and zextload, which
are integer only.
llvm-svn: 24814
2005-12-18 02:48:48 +00:00
5580e69df6
Add constant pool support, including folding into addresses.
...
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]
llvm-svn: 24813
2005-12-18 02:37:35 +00:00
726075fdf8
Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
...
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24812
2005-12-18 02:27:00 +00:00
a983c3df1c
Add initial support for global variables, and fix a bug in addr mode selection
...
where we didn't select the operands.
llvm-svn: 24811
2005-12-18 02:10:39 +00:00
a49b652a62
Claiming that branch targets are registers is not very wholesome. Change them
...
to be basic blocks. Also, add uncond branches.
llvm-svn: 24810
2005-12-18 01:46:58 +00:00
b29957500e
Add unordered comparisons
...
llvm-svn: 24809
2005-12-18 01:41:39 +00:00
e58481be36
Add patterns to the rest of the int condbranches and some of the fp branches
...
llvm-svn: 24808
2005-12-18 01:38:19 +00:00
9cf4bb2867
Add initial conditional branch support. This doesn't actually work yet due
...
to a bug in the scheduler.
llvm-svn: 24807
2005-12-18 01:20:35 +00:00
cf12118965
Simplify code
...
llvm-svn: 24806
2005-12-18 01:03:46 +00:00
00759eac78
Eliminate CMPri, which is a synonym for SUBCCri
...
llvm-svn: 24805
2005-12-17 23:52:08 +00:00
bf0bd99e03
allow custom expansion of BR_CC
...
llvm-svn: 24804
2005-12-17 23:46:46 +00:00
5a6b03c1b8
add fneg,fabs,fsqrt instructions
...
llvm-svn: 24803
2005-12-17 23:20:27 +00:00
32f19262d5
Add patterns for fround/fextend and the funny fsmuld instruction
...
llvm-svn: 24802
2005-12-17 23:14:30 +00:00
06952dfced
Add FP +,-,*,/
...
llvm-svn: 24801
2005-12-17 23:10:46 +00:00
89078880f2
Give patterns to F3_3 instructions
...
llvm-svn: 24800
2005-12-17 23:05:35 +00:00
829572cdca
Implement 64-bit add/sub, make sure to receive and return 64-bit args with
...
the right halves in the right regs
llvm-svn: 24799
2005-12-17 22:55:57 +00:00
ebfa06a2de
implement div and rem
...
llvm-svn: 24798
2005-12-17 22:39:19 +00:00
8eaf9f4cb3
implement MULHU/MULHS for 64-bit multiplies
...
llvm-svn: 24797
2005-12-17 22:30:00 +00:00
4abe9528f9
Add patterns for multiply, simplify Y register handling stuff, add RDY instruction
...
llvm-svn: 24796
2005-12-17 22:22:53 +00:00
2616a0b56f
Make the addressing modes smarter
...
llvm-svn: 24795
2005-12-17 21:25:27 +00:00
19ff62dc67
remove some unused instructions
...
llvm-svn: 24794
2005-12-17 21:13:50 +00:00
e39ab718c0
add andn/orn/xorn patterns. This allows us to compile this:
...
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24793
2005-12-17 21:05:49 +00:00
ea752cc50a
Add support for 64-bit arguments
...
llvm-svn: 24792
2005-12-17 20:59:06 +00:00
6be83f9959
Sparc doesn't have sext_inreg
...
llvm-svn: 24791
2005-12-17 20:50:42 +00:00
d10995cb26
add patterns for FP stores
...
llvm-svn: 24790
2005-12-17 20:47:16 +00:00
490a6edf52
Add [reg+reg] integer stores
...
llvm-svn: 24789
2005-12-17 20:44:36 +00:00
b57bb13253
Add store patterns
...
llvm-svn: 24788
2005-12-17 20:42:55 +00:00
233e044738
add truncstore
...
llvm-svn: 24787
2005-12-17 20:42:29 +00:00
7e7c355154
add fp load patterns, switch rest of loads and stores to use addrmodes
...
llvm-svn: 24786
2005-12-17 20:32:47 +00:00
c4f3a7adea
Add integer load[r+r] forms.
...
llvm-svn: 24785
2005-12-17 20:26:45 +00:00
1c02c45f18
Rename load/store instructions to include an RI suffix
...
llvm-svn: 24784
2005-12-17 20:18:49 +00:00
4fa86e1d55
Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts
...
llvm-svn: 24783
2005-12-17 20:18:24 +00:00
5d15f9ed60
Add basic addressing mode support and one load.
...
llvm-svn: 24782
2005-12-17 20:04:49 +00:00
db8e888fb5
eliminate some redundancy
...
llvm-svn: 24781
2005-12-17 19:47:05 +00:00
5e68639009
Use a combination of sethi and or to build arbitrary immediates.
...
llvm-svn: 24780
2005-12-17 19:41:43 +00:00
8546257435
Use sethi to build large immediates with zeros at the bottom
...
llvm-svn: 24779
2005-12-17 19:37:00 +00:00
7b6f2e879d
Add shift and small immediate support
...
llvm-svn: 24778
2005-12-17 19:07:57 +00:00
30f924e3ca
Add some basic reg-reg instructions
...
llvm-svn: 24777
2005-12-17 18:53:33 +00:00
2edb4b7f99
Add empty patterns to all F3_1 instructions
...
llvm-svn: 24776
2005-12-17 18:49:14 +00:00
1d71248392
Darwin API issue: indirect load of external and weak symbols.
...
llvm-svn: 24775
2005-12-17 09:13:43 +00:00
866cef563b
Add some simple integer patterns. This allows us to compile this:
...
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
llvm-svn: 24774
2005-12-17 08:26:38 +00:00
80a3875bc1
Implement ret with operand, giving us this:
...
int %test(int %A) {
ret int %A
}
llvm-svn: 24773
2005-12-17 08:15:09 +00:00
1136b7a2e0
Add a pattern for 'ret'. This now compiles:
...
void %test() { ret void }
:)
llvm-svn: 24772
2005-12-17 08:08:42 +00:00
1549e4d590
Add empty patterns for F3_2 instructions
...
llvm-svn: 24771
2005-12-17 08:06:43 +00:00
9f1c860e1e
Implement LowerArguments, at least for the first 6 integer args
...
llvm-svn: 24770
2005-12-17 08:03:24 +00:00
4f34e9f7ff
Add the framework for a dag-dag isel
...
llvm-svn: 24769
2005-12-17 07:47:01 +00:00
f3b16bc5a0
Remove a few lines of dead code.
...
llvm-svn: 24768
2005-12-17 07:18:44 +00:00
69b5d17f92
asmprinter done, added crucial missing step
...
llvm-svn: 24767
2005-12-17 07:17:59 +00:00
55f9dbe1ea
Use the AsmPrinter for global variable init printing. This eliminates a
...
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.
llvm-svn: 24766
2005-12-17 07:17:08 +00:00
fb7fd98cd4
Switch constant pool printing over to use the Shared AsmPrinter version
...
llvm-svn: 24765
2005-12-17 07:11:43 +00:00
b808c8e2e4
Use the shared AsmPrinter code for some basic stuff. No functionality
...
change except for fewer .section directives emitted
llvm-svn: 24764
2005-12-17 07:04:29 +00:00
7087cd275b
Added an idea about any_extend for performance tuning.
...
llvm-svn: 24763
2005-12-17 06:54:43 +00:00
9e2af046e4
Convert the remaining instructions over, branches and calls. Fix a couple
...
minor bugs
llvm-svn: 24762
2005-12-17 06:54:41 +00:00
6b669e2680
convert FP instructions to use an asmstring and operand list, allowing FP
...
programs to work on V8 again
llvm-svn: 24761
2005-12-17 06:32:52 +00:00
bc7708c0e8
Added truncate.
...
llvm-svn: 24760
2005-12-17 02:02:50 +00:00
b06925d1dd
Added anyext, modelled as zext on X86.
...
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
e58ab48ccb
Yet another variant of getTargetNode().
...
llvm-svn: 24758
2005-12-17 01:44:51 +00:00
6b76009393
Added some isel ideas.
...
llvm-svn: 24757
2005-12-17 01:25:19 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
0f68322992
Only lower SELECT when using DAG based isel.
...
llvm-svn: 24755
2005-12-17 01:22:13 +00:00
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
...
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
59dc6c553d
Fix VC++ level 4 warnings. Because a base class has declared these private, VC++ complains it cannot automatically generate this methods.
...
llvm-svn: 24751
2005-12-17 00:19:22 +00:00
ea36abe567
Fix VC++ level 4 warnings.
...
llvm-svn: 24750
2005-12-17 00:18:06 +00:00
9504149c1b
Turn on string pooling for smaller binaries.
...
llvm-svn: 24749
2005-12-17 00:14:47 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
887af88ce3
Weak and linkonce global vars should still have a .globl emitted for them
...
llvm-svn: 24747
2005-12-16 21:46:14 +00:00
672578bd94
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
llvm-svn: 24746
2005-12-16 09:19:13 +00:00
9f2c3a7c4e
add some notes
...
llvm-svn: 24745
2005-12-16 07:20:53 +00:00
fa55745cbc
Add a couple more instrs
...
llvm-svn: 24744
2005-12-16 07:18:48 +00:00
e082426ae7
remove some dead code
...
llvm-svn: 24743
2005-12-16 07:16:02 +00:00
70310906e7
asmprint pseudo instrs
...
llvm-svn: 24742
2005-12-16 07:13:26 +00:00
68d064a3a6
Autogenerate asmprinter for F3_2 instructions
...
llvm-svn: 24741
2005-12-16 07:10:02 +00:00
1e777082a0
Switch F3_1 instructions over to use AsmStrings
...
llvm-svn: 24740
2005-12-16 06:52:00 +00:00
4870224a56
Plug in basic hooks for an autogenerated asm printer to fill in.
...
llvm-svn: 24739
2005-12-16 06:34:17 +00:00
34e80f0114
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
...
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it
for regression tests :)
llvm-svn: 24738
2005-12-16 06:25:42 +00:00
0d129ae8b1
A truly trivial testcase to ensure sparcv8 doesn't get completely broken
...
again.
llvm-svn: 24737
2005-12-16 06:24:55 +00:00
b527f48acd
Remove JIT support, which doesn't work.
...
llvm-svn: 24736
2005-12-16 06:06:07 +00:00
1e1ca1e9a5
add some simple operand info
...
llvm-svn: 24735
2005-12-16 06:02:58 +00:00
08a04cb3f2
rename option for consistency with -mcpu -mattr etc
...
llvm-svn: 24734
2005-12-16 05:19:55 +00:00
77e28af47d
rename options
...
llvm-svn: 24733
2005-12-16 05:19:35 +00:00
78e9e10b53
rename option
...
llvm-svn: 24732
2005-12-16 05:19:18 +00:00
3bf72b5c19
Document -mcpu -mattr -triple
...
llvm-svn: 24731
2005-12-16 05:18:53 +00:00
76766cb880
provide an option to override the target triple in a module from the commandline.
...
llvm-svn: 24730
2005-12-16 05:00:21 +00:00
e568b88c98
provide an option to override the target triple in a module from the command
...
line.
llvm-svn: 24729
2005-12-16 04:59:57 +00:00
575751151c
Update the darwin handling of linkonce & weak functions and GV stubs. This
...
should work in all permutations.
llvm-svn: 24728
2005-12-16 00:22:14 +00:00
9f62a2a51d
Don't globalize internal functions
...
llvm-svn: 24727
2005-12-16 00:07:30 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
...
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
83e4407379
Don't create SEXTLOAD/ZEXTLOAD instructions that the target doesn't support
...
if after legalize. This fixes IA64 failures.
llvm-svn: 24725
2005-12-15 19:02:38 +00:00
305c6a73b5
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
...
leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
a2ebc62862
Added constpool, frameindex, and externalsym nodes.
...
llvm-svn: 24723
2005-12-15 08:29:48 +00:00
00fcb0017e
Handling zero extension of 1 bit value.
...
llvm-svn: 24722
2005-12-15 01:02:48 +00:00
bc9344477e
Use MOV8rm to load 1 bit value.
...
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
808f7a8abb
Remove a now unused statistic.
...
llvm-svn: 24720
2005-12-14 22:56:16 +00:00
e37cb604c1
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
llvm-svn: 24719
2005-12-14 22:54:33 +00:00
7853983b40
Add a case for float just to make sure the patterns for both precisions
...
are matching
llvm-svn: 24718
2005-12-14 22:51:13 +00:00
023aef2f31
Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure.
...
llvm-svn: 24717
2005-12-14 22:28:18 +00:00
3db275d996
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
llvm-svn: 24716
2005-12-14 22:07:12 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
8dea0eca2f
Fix printing of the instructions.
...
llvm-svn: 24714
2005-12-14 22:01:07 +00:00
b8be9d1596
Fixed extload type profile. The 4th operand is a ValueType node with type
...
OtherVT, it cannot be compare to type of 1st operand which is an integer type.
llvm-svn: 24713
2005-12-14 19:40:54 +00:00
d39c60fcc8
When folding loads into ops, immediately replace uses of the op with the
...
load. This reduces number of worklist iterations and avoid missing optimizations
depending on folding of things into sext_inreg nodes (which aren't supported by
all targets).
Tested by Regression/CodeGen/X86/extend.ll:test2
llvm-svn: 24712
2005-12-14 19:25:30 +00:00
eaee560c96
new testcase, each function should have one extension instr in it
...
llvm-svn: 24711
2005-12-14 19:24:08 +00:00
4c10e7643f
Remove -start-group and -end-group no-op options, accidentally committed
...
in last patch.
llvm-svn: 24710
2005-12-14 19:08:51 +00:00
7dac1083da
Fix the (zext (zextload)) case to trigger, similarly for sign extends.
...
Allow (zext (truncate)) to apply after legalize if the target supports
AND (which all do).
This compiles
short %foo() {
%tmp.0 = load ubyte* %X ; <ubyte> [#uses=1]
%tmp.3 = cast ubyte %tmp.0 to short ; <short> [#uses=1]
ret short %tmp.3
}
to:
_foo:
movzbl _X, %eax
ret
instead of:
_foo:
movzbl _X, %eax
movzbl %al, %eax
ret
thanks to Evan for pointing this out.
llvm-svn: 24709
2005-12-14 19:05:06 +00:00
8c9e14620f
Fix Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll, a crash on undefined
...
behavior in 126.gcc on big-endian systems.
llvm-svn: 24708
2005-12-14 17:23:59 +00:00
f69abd13d4
new (undefined) testcase, distilled from 126.gcc that scalarrepl crashes on
...
llvm-svn: 24707
2005-12-14 17:23:20 +00:00
f753d1a574
Fix a miscompilation in crafty due to a recent patch
...
llvm-svn: 24706
2005-12-14 07:58:38 +00:00
c273900dd8
Added sext and zext patterns.
...
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
683d8515b1
Added sextld + zextld DAG nodes.
...
llvm-svn: 24703
2005-12-14 02:21:01 +00:00
bce7c47306
Fold (zext (load x) to (zextload x).
...
llvm-svn: 24702
2005-12-14 02:19:23 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
69caef2b78
Prepare support for AltiVec multiply, divide, and sqrt.
...
llvm-svn: 24700
2005-12-13 22:55:22 +00:00
6796b48e51
Adjust the constructor to the Linker class to take an argument that names
...
the module being constructed. This is used to correctly name the module.
Previously the name of the linker tool was used which produces confusing
output when the module identifier is used in an error message.
llvm-svn: 24699
2005-12-13 20:00:37 +00:00
175613adf6
Improve ResolveFunctions to:
...
a) use better local variable names (OldMT -> OldFT) where "M" is used to
mean "Function" (perhaps it was previously "Method"?)
b) print out the module identifier in a warning message so that it is
possible to track down in which module the error occurred.
llvm-svn: 24698
2005-12-13 19:56:51 +00:00
5d4e61dd87
Don't lump the filename and working dir together
...
llvm-svn: 24697
2005-12-13 17:40:33 +00:00
229f0ee6d7
Add load + store folding srl and sra patterns.
...
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
87079884d1
Use the shared asmprinter code for printing special llvm globals
...
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
f0e9aef954
Add a couple more fields, move ctor init list to .cpp file, add support
...
for emitting the ctor/dtor list for common targets.
llvm-svn: 24694
2005-12-13 06:32:10 +00:00
4d80f6e52e
Add ELF and darwin support for static ctors and dtors
...
llvm-svn: 24693
2005-12-13 04:53:51 +00:00
54a11df95d
reindent a loop, unswitch a loop. No functionality changes
...
llvm-svn: 24692
2005-12-13 04:33:58 +00:00
956aef45c9
Lowering constant pool entries on ppc exposed a bug in the recently added
...
ConstantVec legalizing code, which would return constantpool nodes that
were not of the target's pointer type.
llvm-svn: 24691
2005-12-13 03:03:23 +00:00
acec857b1a
Beautify a few patterns.
...
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
89c6db4baf
Some shl patterns which do load + store folding.
...
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
108beceb0f
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
...
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
ddd5ae5a22
Add and, or, and xor patterns which fold load + stores.
...
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
e5a94a03e2
Add inc + dec patterns which fold load + stores.
...
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
bde9e6fca6
Add neg and not patterns which fold load + stores.
...
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
c414d563f0
Missed a couple redundant explicit type casts.
...
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
62e6808aa5
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
...
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
86b2cf22d2
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
...
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
3e52756928
Add some integer mul patterns.
...
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
9e8b633ec1
Accept and ignore prefetches for now
...
llvm-svn: 24678
2005-12-12 22:51:16 +00:00
b42ce7ca63
Fix CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
...
llvm-svn: 24677
2005-12-12 22:27:43 +00:00
1b668bc808
Testcase for a problem that reid ran into
...
llvm-svn: 24676
2005-12-12 22:27:22 +00:00
af3fe8217a
Add some sub patterns.
...
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
...
base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
...
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
cd54254af3
fix FP selects
...
llvm-svn: 24672
2005-12-12 20:30:09 +00:00
d6b17765e4
remove some never-completed and now-obsolete code.
...
llvm-svn: 24671
2005-12-12 20:12:20 +00:00
e80248b378
Add a few more add / store patterns. e.g. ADD32mi8.
...
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
b8296181e0
restore a more restricted select
...
llvm-svn: 24668
2005-12-12 17:43:52 +00:00
3b0a62d8a5
Implement a little hack for parity with GCC on crafty. This speeds up
...
186.crafty by about 16% (from 15.109s to 13.045s) on my system.
This turns allocas with unions/casts into scalars. For example crafty has
something like this:
union doub {
unsigned short i[4];
long long d;
};
int f(long long a) {
return ((union doub){.d=a}).i[1];
}
Instead of generating loads and stores to an alloca, we now promote the
whole thing to a scalar long value.
This implements: Transforms/ScalarRepl/AggregatePromote.ll
llvm-svn: 24667
2005-12-12 07:19:13 +00:00
cf510b36c1
new testcase: sra should be able to eliminate all of these alloca's, despite
...
the presense of pointer casts
llvm-svn: 24666
2005-12-12 07:18:59 +00:00
08dbd94632
Send an indicator to llvm-testresults if the build failed
...
llvm-svn: 24665
2005-12-11 19:55:39 +00:00
a4c6cc5af4
Fix typo :(
...
llvm-svn: 24664
2005-12-11 18:43:13 +00:00
f1a54c0d14
Minor tweak to get isel opt
...
llvm-svn: 24663
2005-12-11 09:05:13 +00:00
254e0a842f
add selectcc
...
llvm-svn: 24662
2005-12-11 08:35:54 +00:00
090eed0483
Remove type casts that are no longer needed
...
llvm-svn: 24661
2005-12-11 07:45:47 +00:00
e6f2c82073
Realize the constant pool & global addrs must always be ptr type
...
llvm-svn: 24660
2005-12-11 07:45:04 +00:00
3d9559fedc
Fix the JIT failures from last night.
...
llvm-svn: 24659
2005-12-11 07:37:41 +00:00
20d0b81c04
FP select improvements (and likely breakage), oh and crazy people might want to *return* floating point values. Don't see why myself
...
llvm-svn: 24658
2005-12-11 03:54:31 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
3c5198336c
Use SDTCisPtrTy type property for store address.
...
llvm-svn: 24656
2005-12-10 01:59:36 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
0d6cfee704
* Added X86 store patterns.
...
* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
dadc1057ac
Added new getNode and getTargetNode variants for X86 stores.
...
llvm-svn: 24653
2005-12-10 00:37:58 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
27656ac89c
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
...
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
llvm-svn: 24650
2005-12-09 22:58:42 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
275a3ed80c
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
...
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
a6f835f5a0
Avoid emitting two tabs when switching to a named section
...
llvm-svn: 24646
2005-12-09 19:28:49 +00:00
e0f5f8e43c
Teach the PPC backend about the ctor and dtor list when not using __main and
...
linking the entire program into one bc file.
llvm-svn: 24645
2005-12-09 18:24:29 +00:00
268d457b69
Teach legalize how to promote sext_inreg to fix a problem Andrew pointed
...
out to me.
llvm-svn: 24644
2005-12-09 17:32:47 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
87bf2234b5
it helps if your conditionals are not reversed
...
llvm-svn: 24641
2005-12-09 00:45:42 +00:00
be73d6eece
improve code insertion in two ways:
...
1. Only forward subst offsets into loads and stores, not into arbitrary
things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
allowing us to fold the cast away (improving cases when the cast is
from an alloca or global).
This hasn't been fully tested, but does appear to further reduce register
pressure and improve code. Lets let the testers grind on it a bit. :)
llvm-svn: 24640
2005-12-08 08:00:12 +00:00
29e6c3dbf9
Add another important case we miss
...
llvm-svn: 24639
2005-12-08 07:13:28 +00:00
790af6d18f
Added support for ComplexPattern.
...
llvm-svn: 24638
2005-12-08 04:28:48 +00:00
f039648614
Added explicit type field to ComplexPattern.
...
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
...
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
ae89d862f5
Fix a crash where ConstantVec nodes were being generated with the wrong
...
type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T, <int 1, int 2, int 3, int 4>
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
llvm-svn: 24633
2005-12-07 19:48:11 +00:00
57c882edf8
Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
...
if the target supports the resultant sextinreg
llvm-svn: 24632
2005-12-07 18:02:05 +00:00
3225733e65
X86 doesn't support sextinreg for 8-bit things either.
...
llvm-svn: 24631
2005-12-07 17:59:14 +00:00
cbd3d01a43
Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg
...
when the types match up. This allows the X86 backend to compile:
sbyte %toggle_value(sbyte* %tmp.1) {
%tmp.2 = load sbyte* %tmp.1
ret sbyte %tmp.2
}
to this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
ret
instead of this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
movsx %EAX, %AL
ret
noticed in Shootout/objinst.
-Chris
llvm-svn: 24630
2005-12-07 07:11:03 +00:00
30aa5f735f
Remove a now-dead map, patch by Saem Ghani, thanks!
...
llvm-svn: 24629
2005-12-07 05:41:44 +00:00
26473b6b58
fix divide and remainder
...
llvm-svn: 24628
2005-12-06 23:27:39 +00:00
de085f0165
Silence another annoying GCC warning
...
llvm-svn: 24627
2005-12-06 20:56:18 +00:00
312e65568c
This solves the problem of the CBE renaming symbols that start with . but the assembly side still trying to reference them by their old names. Should be safe untill we hit a language front end that lets you specify such a name.
...
llvm-svn: 24626
2005-12-06 20:51:30 +00:00
973cd1c845
more decent branches for FP. I might have to make some intermediate nodes to actually be able to use the DAG for FPcmp
...
llvm-svn: 24625
2005-12-06 20:43:30 +00:00
29b7ef0065
OK, this does wonders for broken stuff
...
llvm-svn: 24624
2005-12-06 20:40:34 +00:00
e3cccc938b
Added comment for removing assert
...
llvm-svn: 24623
2005-12-06 18:16:08 +00:00
a69fcbdeb8
Collapsing node if variable length struct with final field of length zero
...
llvm-svn: 24621
2005-12-06 18:04:30 +00:00
1473162af0
Handling of zero length last fields in struct used for growing it arbitrarily
...
llvm-svn: 24620
2005-12-06 18:01:20 +00:00
d490d4f023
Fix test/Regression/Linker/2005-12-06-AppendingZeroLengthArrays.ll and
...
PR662. Thanks to Markus for providing me with a ton of files to
reproduce the problem!
llvm-svn: 24619
2005-12-06 17:30:58 +00:00
98dcd12c28
new testcase for PR662
...
llvm-svn: 24618
2005-12-06 17:29:54 +00:00
cfe67e1318
Implement external storage for post-order iteration, implementing PR267
...
Patch by Saem Ghani, thanks!
llvm-svn: 24617
2005-12-06 07:05:27 +00:00
41b1cdc771
Teach the SelectionDAG ISel how to turn ConstantPacked values into
...
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
llvm-svn: 24616
2005-12-06 06:18:55 +00:00
fea33f7e64
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
2005-12-06 02:10:38 +00:00
e788bbf6ef
added instructions with inverted immediates
...
llvm-svn: 24614
2005-12-06 00:33:53 +00:00
08c4a775e6
yea, it helps to have your path set right when testing
...
llvm-svn: 24613
2005-12-05 23:41:45 +00:00
3c7c4d7508
These never trigger, but whatever
...
llvm-svn: 24612
2005-12-05 23:19:44 +00:00
c0c190239d
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
...
llvm-svn: 24611
2005-12-05 23:09:43 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
5bfcd1e63a
move this over to the dag
...
llvm-svn: 24609
2005-12-05 20:50:53 +00:00
077200737c
getRawValue zero extens for unsigned values, use getsextvalue so that we
...
know that small negative values fit into the immediate field of addressing
modes.
llvm-svn: 24608
2005-12-05 18:23:57 +00:00
9410433966
fix constant pool loads
...
llvm-svn: 24607
2005-12-05 17:51:02 +00:00
3539778883
Fix the #1 code quality problem that I have seen on X86 (and it also affects
...
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
llvm-svn: 24606
2005-12-05 07:10:48 +00:00
7d4d93c52c
Add a flag to Module::getGlobalVariable to allow it to return vars with
...
internal linkage.
Patch provided by Evan Jones, thanks!
llvm-svn: 24604
2005-12-05 05:30:21 +00:00
ca18d19210
attribute((used)) is now supported
...
llvm-svn: 24603
2005-12-05 05:23:06 +00:00
165998207e
Wrap a long line, never internalize llvm.used.
...
llvm-svn: 24602
2005-12-05 05:07:38 +00:00
b0e9741022
New testcase for PR660
...
llvm-svn: 24601
2005-12-05 04:48:12 +00:00
7b43664aa0
testcase for PR664
...
llvm-svn: 24600
2005-12-05 03:22:46 +00:00
3c0b8f577d
Several things:
...
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly. The port number really
*is* a 16-bit value, but the patterns should only match if the number
is 0-255. Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
i8, not an i16 as they were believed to be before. This previous fib
stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.
llvm-svn: 24599
2005-12-05 02:40:25 +00:00
282c2af4d8
On some targets (e.g. X86), shift amounts are not the same as the value
...
being shifted. Don't assume they are.
llvm-svn: 24598
2005-12-05 02:37:26 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
3717b4c830
Add some methods
...
llvm-svn: 24596
2005-12-05 02:35:08 +00:00
c54cddd25b
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
...
llvm-svn: 24595
2005-12-05 02:34:29 +00:00
f3322af5c6
Add some explicit type casts so that tblgen knows the type of the shift
...
amount, which is not necessarily the same as the type being shifted.
llvm-svn: 24594
2005-12-05 02:34:05 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
efc86f5f7a
The basic fneg cases are already autogen'd
...
llvm-svn: 24592
2005-12-04 19:04:38 +00:00
f979794717
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
...
improvements.
llvm-svn: 24591
2005-12-04 19:01:59 +00:00
fd857daa0d
Finish moving uncond br over to .td file, remove from .cpp file.
...
llvm-svn: 24590
2005-12-04 18:48:01 +00:00
d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
...
llvm-svn: 24589
2005-12-04 18:42:54 +00:00
95cb763818
Added isel patterns for RET, JMP, and WRITEPORT.
...
llvm-svn: 24588
2005-12-04 08:19:43 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
e8531381e2
* Added instruction property hasCtrlDep for those which r/w control-flow
...
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
llvm-svn: 24586
2005-12-04 08:13:17 +00:00
7e79292fef
Fix PR672 another way which should be more robust
...
llvm-svn: 24585
2005-12-04 06:03:50 +00:00
394350dcca
new testcase, for PR672
...
llvm-svn: 24584
2005-12-04 06:03:25 +00:00
8782b782cd
dbg.stoppoint returns a value, don't forget to init it
...
llvm-svn: 24583
2005-12-03 18:50:48 +00:00
3339c6a1f6
expand testcase, which has been in my tree for a while now
...
llvm-svn: 24582
2005-12-03 18:26:41 +00:00
2820b8c855
Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
...
llvm-svn: 24581
2005-12-03 18:25:58 +00:00
2492b74330
new testcase, miscompiled by simplifycfg. This has been distilled from Ptrdist/bc
...
llvm-svn: 24580
2005-12-03 18:25:32 +00:00
bd23d34be0
Fix a bug in the testcase
...
llvm-svn: 24579
2005-12-03 17:20:57 +00:00
ecfc7e56c5
Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.
...
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on. Given a clean nightly tester run, we should be able to turn it
on by default!
llvm-svn: 24578
2005-12-03 07:15:55 +00:00
5d7a0a3aee
new testcase for PR672
...
llvm-svn: 24577
2005-12-03 07:14:47 +00:00
352630141c
Revert my previous patch which broke due to lazy streaming of functions
...
from .bc files.
llvm-svn: 24575
2005-12-02 19:00:22 +00:00
Evan Cheng