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Author SHA1 Message Date
Jim Grosbach 9398141c48 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Bill Wendling 265328baf6 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
llvm-svn: 141716
 2011-10-11 21:40:47 +00:00
Cameron Zwarich 1a761dcfbd Fix PR11106 by correcting a typo that has been in the code for over a year. This 
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

llvm-svn: 141713
 2011-10-11 21:26:40 +00:00
Jim Grosbach 8c799c9826 Update test for r141704. 
llvm-svn: 141705
 2011-10-11 20:18:50 +00:00
Devang Patel 453d401a51 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
 2011-10-11 18:09:58 +00:00
Nadav Rotem 3283793c9a Add support for legalization of vector SHL/SRA/SRL instructions 
llvm-svn: 141667
 2011-10-11 14:36:35 +00:00
Nick Lewycky 3e01bd3b60 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
 2011-10-11 06:58:11 +00:00
Craig Topper 603cc851f8 Test case for X86 LZCNT instruction selection. 
llvm-svn: 141652
 2011-10-11 06:47:01 +00:00
Craig Topper 271064e873 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Cameron Zwarich ab3a9b3baf Add a test for PR10565. 
llvm-svn: 141647
 2011-10-11 06:10:37 +00:00
Cameron Zwarich d7515ccc47 Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's 
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

llvm-svn: 141646
 2011-10-11 06:10:30 +00:00
Bill Wendling 288ff0ec82 Test simplification that Ana Pazos noticed. 
llvm-svn: 141644
 2011-10-11 04:43:15 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Nick Lewycky 29e7b315ac Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641
 2011-10-11 03:54:50 +00:00
NAKAMURA Takumi ba38717f34 test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts. 
llvm-svn: 141640
 2011-10-11 03:41:03 +00:00
Andrew Trick f9201c572e Move replaceCongruentIVs into SCEVExapander and bias toward "expanded" 
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.

llvm-svn: 141633
 2011-10-11 02:28:51 +00:00
Akira Hatanaka 8782734bcc Test cases for 64-bit load and store instructions. 
llvm-svn: 141631
 2011-10-11 01:52:31 +00:00
Lang Hames 44c78f809b Added a testcase for r141599, rdar://problem/10063881. 
llvm-svn: 141628
 2011-10-11 01:32:10 +00:00
Bill Wendling 9449b8b9d2 Add testcase for PR11107. 
llvm-svn: 141607
 2011-10-11 00:26:57 +00:00
Devang Patel 478d5bc0d0 Revert r141569 and r141576. 
llvm-svn: 141594
 2011-10-10 23:18:02 +00:00
Bill Wendling a7d697e4a6 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Eli Friedman 8ec0897db6 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Nick Lewycky fcf8462583 Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.

llvm-svn: 141579
 2011-10-10 21:21:34 +00:00
Devang Patel 2689f95875 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
llvm-svn: 141576
 2011-10-10 20:32:03 +00:00
Nadav Rotem 814598563f Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Devang Patel e554d5995b Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
 2011-10-10 19:09:20 +00:00
Benjamin Kramer 42c0330a79 X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
llvm-svn: 141563
 2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen b253f490c3 Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
 2011-10-10 18:30:16 +00:00
Bill Wendling 47aac51043 Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Benjamin Kramer e7ae31cc25 XFAIL tblgen tests on leak checkers. 
llvm-svn: 141533
 2011-10-10 13:09:59 +00:00
Bill Wendling ea662bb32f When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
 2011-10-10 07:24:23 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen 729abd360e Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen b81dcdef7b Add missing test case for r141410. 
llvm-svn: 141498
 2011-10-08 18:06:54 +00:00
Andrew Trick ce0cb3a101 Unit test for LSR phi reuse in r141442. 
llvm-svn: 141472
 2011-10-08 02:34:51 +00:00
Michael J. Spencer ba4a362276 llvm-objdump: Add relocation and archive support. 
llvm-svn: 141451
 2011-10-08 00:18:30 +00:00
Jim Grosbach c87d60a58c Enable ARM mode VDUP(scalar) tests. 
llvm-svn: 141447
 2011-10-07 23:57:03 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
David Greene 33f619971f Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

llvm-svn: 141378
 2011-10-07 18:25:05 +00:00
Evan Cheng 74db300f37 High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
llvm-svn: 141371
 2011-10-07 17:21:44 +00:00
Bob Wilson 8decdc472f Reenable tail calls for iOS 5.0 and later. 
llvm-svn: 141370
 2011-10-07 17:17:49 +00:00
Bob Wilson bc1589945d Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
llvm-svn: 141368
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov 318d6bae80 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!

llvm-svn: 141365
 2011-10-07 16:15:08 +00:00
Duncan Sands c52af46484 Teach GVN to also propagate switch cases. For example, in this code 
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.

llvm-svn: 141360
 2011-10-07 08:29:06 +00:00
Craig Topper d9cfddc5cd Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
llvm-svn: 141358
 2011-10-07 07:02:24 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Jim Grosbach 0947102623 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
llvm-svn: 141321
 2011-10-06 22:04:05 +00:00
Jim Grosbach 4887469138 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141318
 2011-10-06 21:32:50 +00:00
Jim Grosbach ceb4c7523f Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141316
 2011-10-06 21:28:30 +00:00