873f7aff62
Make sure CMake can build the files added by my previous commit.
...
llvm-svn: 106178
2010-06-16 23:52:37 +00:00
842eb0905e
Add preliminary clang attribute generation support.
...
The attribute class generation support is still somewhat limited.
See the accompanying clang commit for more details.
llvm-svn: 106174
2010-06-16 23:45:50 +00:00
e3864cc15e
format and 80-column cleanup
...
llvm-svn: 106173
2010-06-16 23:45:49 +00:00
77a4a56251
let the '!eq' expression support 'int' and 'bit' types
...
llvm-svn: 106171
2010-06-16 23:24:12 +00:00
e94f1ded24
remove trailing whitespace
...
llvm-svn: 106164
2010-06-16 22:41:09 +00:00
1e69f3c7be
Revert r106117, which was the result of me misreading the C++98/03
...
specification.
llvm-svn: 106162
2010-06-16 22:32:18 +00:00
2334144e6e
Don't attempt preserving conservative kill flags. We were doing it wrong.
...
This is before LiveVariables anyway, where these kill flags are recalculated.
llvm-svn: 106157
2010-06-16 22:11:08 +00:00
01ac8f9fc0
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
...
now, so there's no need to disable them.
llvm-svn: 106155
2010-06-16 21:34:01 +00:00
74892d4f1f
In progress on 32-bit addends.
...
llvm-svn: 106154
2010-06-16 21:32:38 +00:00
207cd4bbd7
Allow a register to be redefined multiple times in a basic block.
...
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.
Here is an example of chained INSERT_SUBREGs that we can handle now:
68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
register: %reg1040 +[70,134:0)
76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78)
84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86)
92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)
rdar://problem/8096390
llvm-svn: 106152
2010-06-16 21:29:40 +00:00
fd3b4e7390
A few more places where SCEVExpander bits need to skip over debug intrinsics
...
when iterating through instructions. Yet more work for rdar://7797940
llvm-svn: 106149
2010-06-16 21:13:38 +00:00
2c8b829238
modify so the test doesn't drop an output file in the test source directory.
...
The test should also likely have some FileCheck bits to validate the
output(?).
llvm-svn: 106146
2010-06-16 21:07:06 +00:00
ede8e6d2f0
MC/Mach-O: Rewrite atom association to be a final pass we do in Finish(), instead of tracking as part of emission.
...
- This allows sharing more code with the MCObjectStreamer.
llvm-svn: 106143
2010-06-16 20:04:32 +00:00
aa627c39e4
MC: Simplify MCAssembler::isSymbolLinkerVisible to only take an MCSymbol.
...
llvm-svn: 106142
2010-06-16 20:04:29 +00:00
b2347fe504
MC: Lift SwitchSection() and Finish() into MCObjectStreamer.
...
llvm-svn: 106141
2010-06-16 20:04:25 +00:00
8a3c9d9bc4
MC: Factor out an MCObjectStreamer class, which will be shared by the concrete
...
object file format writers.
llvm-svn: 106140
2010-06-16 20:04:22 +00:00
79b0da30fb
Be specific. Use FileCheck.
...
llvm-svn: 106135
2010-06-16 19:39:45 +00:00
a20e2dfe86
Make sure that simplify libcalls does not replace a call with one calling
...
convention with a new call with a different calling convention.
llvm-svn: 106134
2010-06-16 19:34:01 +00:00
6c0da25129
add FIXME
...
llvm-svn: 106126
2010-06-16 18:45:08 +00:00
e3721dd27c
This requires more investigation. Unblock buildbots for now.
...
llvm-svn: 106122
2010-06-16 18:19:49 +00:00
37e4f98cb6
Update test to explicitly capture llc output.
...
llvm-svn: 106121
2010-06-16 18:04:12 +00:00
d71bd63600
Improve comment to include that the use of a preg is also verboten in this situation.
...
llvm-svn: 106119
2010-06-16 18:01:31 +00:00
21bc129db3
Eliminate a redundant "typename" keyword
...
llvm-svn: 106117
2010-06-16 17:42:01 +00:00
41476410c9
TODO--
...
llvm-svn: 106102
2010-06-16 15:47:00 +00:00
a13bd20396
simplify-libcalls: fold strncmp(x, y, 1) -> memcmp(x, y, 1)
...
The memcmp will be optimized further and even the pathological case
'strstr(x, "x") == x' generates optimal code now.
llvm-svn: 106097
2010-06-16 10:30:29 +00:00
f128bdcb55
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
...
llvm-svn: 106091
2010-06-16 07:35:02 +00:00
d119da54de
Check function pointer first, before comparing function names.
...
llvm-svn: 106088
2010-06-16 06:42:02 +00:00
a6d20f446f
Use separate named MDNode to hold each function's local variable info.
...
This speeds up local variable handling in DwarfDebug.
llvm-svn: 106075
2010-06-16 00:53:55 +00:00
b672ab9b53
Don't emit the linkage for initializer label for mach-o tls.
...
llvm-svn: 106073
2010-06-16 00:27:30 +00:00
2092dc2acd
Fix indentation.
...
llvm-svn: 106072
2010-06-16 00:26:36 +00:00
8c0cf0994d
Create a more targeted fix for not sinking instructions into a range where it
...
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.
llvm-svn: 106066
2010-06-15 23:46:31 +00:00
6c4d63e1a5
For 32-bit non-pic tlv mach-o addressing we don't need a pic base or
...
a relative address.
llvm-svn: 106064
2010-06-15 23:08:42 +00:00
9b5005cd4b
Added a comment.
...
llvm-svn: 106063
2010-06-15 23:06:30 +00:00
a86c2bdd2c
Some more work on mach-o TLV relocations.
...
llvm-svn: 106062
2010-06-15 22:59:05 +00:00
438c35b5d1
Add file missing from previous commit.
...
llvm-svn: 106058
2010-06-15 22:24:08 +00:00
8105144fcd
Fix 80col violations, remove trailing whitespace, and clarify a comment.
...
llvm-svn: 106057
2010-06-15 22:18:54 +00:00
1115afb092
Update test to match recent llvm-gcc change.
...
llvm-svn: 106056
2010-06-15 22:16:40 +00:00
26cefa5e11
Make VC++ happy
...
llvm-svn: 106054
2010-06-15 22:10:31 +00:00
44f9dfc9cf
Next round of tail call changes. Register used in a tail
...
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
llvm-svn: 106053
2010-06-15 22:08:33 +00:00
ec2e964fd6
Remove the local register allocator.
...
Please use the fast allocator instead.
llvm-svn: 106051
2010-06-15 21:58:33 +00:00
89456b2612
Reapply 105986 with fix for bug pointed out by Jakob:
...
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info. I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.
llvm-svn: 106049
2010-06-15 21:36:43 +00:00
f9d8e17ec5
fix PR7380: use 'test' instead of shell builtins. This improves
...
portability to Solaris 10, which apparently doesn't support
[ foo -ot bar ]
llvm-svn: 106048
2010-06-15 21:35:22 +00:00
1118860e3a
simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0
...
llvm-svn: 106047
2010-06-15 21:34:25 +00:00
ae591be4e9
Set the mtriple in some tests so that they use AAPCS.
...
llvm-svn: 106041
2010-06-15 20:42:00 +00:00
7a84689cc5
Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen!
...
llvm-svn: 106038
2010-06-15 20:29:05 +00:00
e22295e8a6
fpcmp: Fix bug where fpcmp wouldn't early exit when files obviously differ and
...
no tolerance is set.
llvm-svn: 106033
2010-06-15 19:20:30 +00:00
b645fa13a9
fpcmp: Fix a possible infinite loop when comparing something like:
...
1..19 ok
to
1..20 o k
(yes, the odd space is necessary).
llvm-svn: 106032
2010-06-15 19:20:28 +00:00
874c92bd47
fix fastisel to handle GS and FS relative pointers. Patch by
...
Nelson Elhage!
llvm-svn: 106031
2010-06-15 19:08:40 +00:00
f3f7a770b7
Add basic support for NEON modified immediates besides VMOV.
...
llvm-svn: 106030
2010-06-15 19:05:35 +00:00
5a24a56e1e
Remove the arm_aapcscc marker from the tests. It is the default
...
for the linux targets.
llvm-svn: 106029
2010-06-15 19:04:29 +00:00
146f130d1f
disable SmallVectorImpl's copy constructor. This prevents a class
...
of base class slicing bugs reported on irc
llvm-svn: 106028
2010-06-15 18:59:43 +00:00
fc7d739422
IfConversion's AnalyzeBlocks method always returns false; clean it up.
...
llvm-svn: 106027
2010-06-15 18:57:15 +00:00
c964585ff8
fix naming
...
llvm-svn: 106024
2010-06-15 18:53:34 +00:00
6e54c908e0
Fix an exotic bug that only showed up in an internal test case.
...
SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a
copy is coalescable, and in very rare cases it can return true where LHS is not
live - the coalescable copy can come from an alias of the physreg in LHS.
llvm-svn: 106021
2010-06-15 18:49:14 +00:00
5947573f39
Fix a comment typo.
...
llvm-svn: 106015
2010-06-15 18:19:27 +00:00
a8b941c21b
Remove stray semi-colon.
...
llvm-svn: 106009
2010-06-15 17:47:24 +00:00
de94e66234
Add some missing checks for the case where the extract_subregs are
...
combined to an insert_subreg, i.e., where the destination register is larger
than the source. We need to check that the subregs can be composed for that
case in a symmetrical way to the case when the destination is smaller.
llvm-svn: 106004
2010-06-15 17:27:54 +00:00
246e9a07a2
Avoid processing early clobbers twice in RegAllocFast.
...
Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.
This fixes PR7382.
llvm-svn: 105998
2010-06-15 16:20:57 +00:00
82eca35b3e
Add CoalescerPair helper class.
...
Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:
- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.
CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.
The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.
llvm-svn: 105997
2010-06-15 16:04:21 +00:00
0904134252
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
...
llvm-svn: 105994
2010-06-15 14:50:42 +00:00
a55b8877e6
Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
...
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues. This makes a pretty noticable difference
in our testcases where reg_sequences are used. I've updated one test to
check that we no longer emit the unnecessary subreg moves.
llvm-svn: 105991
2010-06-15 05:56:31 +00:00
1478142485
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
...
llvm-svn: 105990
2010-06-15 05:51:27 +00:00
3f253d2353
Revert 105986; looks like I'd better try bootstrapping.
...
llvm-svn: 105988
2010-06-15 04:55:06 +00:00
d52caa5244
Update CMake build.
...
llvm-svn: 105987
2010-06-15 04:08:14 +00:00
c338ef2b65
The form of BuildMI used for TAILJMPr was changing the register
...
containing the target address, an input, into an output. I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.
llvm-svn: 105986
2010-06-15 03:13:49 +00:00
f14e08b01b
Make sure to skip dbg_value instructions when finding an insertion point for
...
the combined load/store instruction. rdar://7797940
llvm-svn: 105982
2010-06-15 00:41:09 +00:00
c8c2efa7f7
Add missing include to unbreak the build.
...
llvm-svn: 105971
2010-06-14 22:44:26 +00:00
24fdd22766
generate better code in CheckComplexPattern
...
llvm-svn: 105970
2010-06-14 22:33:34 +00:00
5b2b504038
Rename functions referring to VMOV immediates to refer to NEON "modified
...
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
llvm-svn: 105969
2010-06-14 22:19:57 +00:00
412800d346
More dbg_value cleanup so the presence of debug info doesn't affect code-gen.
...
Make sure to skip the dbg_value instructions when moving dups out of the
diamond. rdar://7797940
llvm-svn: 105965
2010-06-14 21:30:32 +00:00
77b6d01906
Don't produce output only if *all* files are unused.
...
llvm-svn: 105962
2010-06-14 21:20:52 +00:00
078f4cec21
- Do away with SimpleHazardRecognizer.h. It's not used and offers little value.
...
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.
llvm-svn: 105959
2010-06-14 21:06:53 +00:00
00ab615406
apparently lots of dupes.
...
llvm-svn: 105956
2010-06-14 20:19:03 +00:00
a397ada078
Avoid uncessary array copying.
...
llvm-svn: 105955
2010-06-14 20:18:40 +00:00
faa7bdccbf
fix a nasty bug where we were not treating available_externally
...
symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
llvm-svn: 105954
2010-06-14 20:11:56 +00:00
bbb798c7d1
remove old test.
...
llvm-svn: 105953
2010-06-14 20:07:43 +00:00
b30f87b74e
rename test
...
llvm-svn: 105952
2010-06-14 20:07:34 +00:00
329ea064ed
jump threading can't split a critical edge from an indirectbr. This
...
fixes PR7356.
llvm-svn: 105950
2010-06-14 19:45:43 +00:00
37b827fd11
Test case for Radar 8004649.
...
llvm-svn: 105949
2010-06-14 18:37:04 +00:00
62d6f947d5
Fix a comment typo.
...
llvm-svn: 105944
2010-06-14 18:29:23 +00:00
58c09b2859
fix a -Wbool-conversions warning from clang.
...
llvm-svn: 105943
2010-06-14 18:28:57 +00:00
0fc88efda3
fix a -Wbool-conversions warning from clang.
...
llvm-svn: 105942
2010-06-14 18:28:34 +00:00
e42d72309b
Honor the SDKROOT setting when building llvm.
...
Radar 7894069.
llvm-svn: 105938
2010-06-14 17:56:25 +00:00
ba1f1fcae5
Add back some possible optimizations for va_arg, with wording that makes it
...
more clear what exactly is missing.
llvm-svn: 105934
2010-06-14 07:03:30 +00:00
4f475d07ba
Update html tutorial docs to match api changes.
...
llvm-svn: 105933
2010-06-14 06:09:39 +00:00
95f5652e2d
Make kaleidoscope use fp add/sub/mul.
...
Patch by Patrick Flannery!
llvm-svn: 105932
2010-06-14 06:03:16 +00:00
ac2aac1860
Add the last of the SemaChecking-gen code.
...
llvm-svn: 105929
2010-06-14 05:17:23 +00:00
6e42d53cb3
Test case for r105914.
...
llvm-svn: 105915
2010-06-13 16:16:54 +00:00
b82de426de
SimplifyCFG: don't turn volatile stores to null/undef into unreachable. Fixes PR7369.
...
llvm-svn: 105914
2010-06-13 14:35:54 +00:00
c49ea3c50e
Let SmallVector take advantage of LiveRange's podness.
...
llvm-svn: 105913
2010-06-13 12:52:38 +00:00
444e9f0a35
Add a helping of comments
...
Add code for generating bits of semachecking
llvm-svn: 105907
2010-06-13 04:47:03 +00:00
e302f833e1
Merge getStoreRegOpcode and getLoadRegOpcode.
...
llvm-svn: 105900
2010-06-12 20:13:29 +00:00
250a21b79b
tests: Run macho-dump with binary unbuffered streams on Windows, I can't find a Python 2.6 way to change stdin to binary.
...
llvm-svn: 105894
2010-06-12 17:05:28 +00:00
edcc628289
tests: Make macho-dump.bat actually work.
...
llvm-svn: 105891
2010-06-12 16:21:54 +00:00
12225eb687
tests: Propogate LLVM_SRC_ROOT and PYTHON_EXECUTABLE environment variables to tests.
...
llvm-svn: 105890
2010-06-12 16:21:19 +00:00
0892ee503a
lit: Replace /dev/null in scripts with temporary files on Windows.
...
llvm-svn: 105888
2010-06-12 16:00:10 +00:00
2ed39551a7
improve verifier error about unterminated block to include
...
function name, patch by Yuri
llvm-svn: 105887
2010-06-12 15:50:24 +00:00
05466ef7eb
declare a class with 'class' instead of struct to avoid tag mismatch
...
warnings, and don't shift by a bool. Patch by Rizky Herucakra!
llvm-svn: 105886
2010-06-12 15:46:56 +00:00
e17e4aea2a
Add README entry; based on testcase from Bill Hart.
...
llvm-svn: 105878
2010-06-12 05:54:27 +00:00
ada854f8b6
make the avx intrinsics 3 address
...
llvm-svn: 105876
2010-06-12 03:12:14 +00:00
b90b010a2d
Add generic vector support for bitselect & element byteswap
...
llvm-svn: 105874
2010-06-12 03:09:49 +00:00
f203703467
Add some basic fp intrinsics for AVX
...
llvm-svn: 105873
2010-06-12 02:38:32 +00:00
5d6103318a
When performing the Horrible Hack(tm-Duncan) on the EH code to convert a
...
clean-up to a catch-all after inlining, take into account that there could be
filter IDs as well. The presence of filters don't mean that the selector catches
anything. It's just metadata information.
llvm-svn: 105872
2010-06-12 02:34:29 +00:00
a714ea0f7d
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
...
llvm-svn: 105870
2010-06-12 01:53:48 +00:00
b06f54b852
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
...
Handle OpSize TSFlag for AVX
llvm-svn: 105869
2010-06-12 01:23:26 +00:00
e60273fd70
Allow target to provide its own hazard recognizer to post-ra scheduler.
...
llvm-svn: 105862
2010-06-12 00:12:18 +00:00
cb1fe56fd9
Code formatting.
...
llvm-svn: 105861
2010-06-12 00:11:53 +00:00
8947c32493
Add some comments about REX fields
...
llvm-svn: 105860
2010-06-12 00:03:52 +00:00
fd5458d4bd
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
...
Introduce the VEX_X field
llvm-svn: 105859
2010-06-11 23:50:47 +00:00
c85504540e
lit: Add a forgotten default argument.
...
llvm-svn: 105858
2010-06-11 23:47:36 +00:00
56b093f572
tests: Add wrapper script for calling macho-dump on Win32.
...
llvm-svn: 105856
2010-06-11 23:29:48 +00:00
43c2cb63ae
lit: When running Tcl style tests on Windows, substitute slashes to avoid Tcl
...
quoting problems. Not particularly ideal, but should work ok. Based on a patch by
Michael Spencer!
llvm-svn: 105855
2010-06-11 23:27:45 +00:00
f07d33d8f1
Add a missing bitcast. This code used to only handle conversions between
...
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
llvm-svn: 105845
2010-06-11 22:45:25 +00:00
70883c32ec
llvm-mc: Don't set NO_INSTALL on llvm-mc.
...
llvm-svn: 105837
2010-06-11 22:00:08 +00:00
6eae520de9
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
llvm-svn: 105836
2010-06-11 21:34:50 +00:00
afe54f1625
Support for nested functions/classes in debug output. (Again.) Radar 7424645.
...
llvm-svn: 105828
2010-06-11 20:08:44 +00:00
6111abf8ad
Delete duplicate function.
...
llvm-svn: 105827
2010-06-11 20:05:01 +00:00
b9639aaed4
Define ContextualFoldingSet, which stores a context parameter to pass down to
...
the Profile method. Currently this only works with the default FoldingSetTraits
implementation.
The point of this is to allow nodes to not store context values which are only
used during profiling. A better solution would thread this value through the
folding algorithms, but then those would need to be (1) templated and
(2) non-opaque.
llvm-svn: 105819
2010-06-11 11:06:44 +00:00
0e915300e3
Add support for polynomial type, for polynomial multiply
...
llvm-svn: 105792
2010-06-10 18:06:07 +00:00
a349d522f7
Avoid "variable 'bits' set but not used [-Wunused-but-set-variable]"
...
warnings with gcc-4.6, by not setting bits when the result is not
used.
llvm-svn: 105790
2010-06-10 16:23:15 +00:00
9943850884
Avoid many "variable 'Sub' set but not used [-Wunused-but-set-variable]" warnings
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with gcc-4.6. The warning is wrong, since Sub *is* used (perhaps gcc is confused
because the use of Sub is constant folded away?), but since it is trivial to avoid,
and massively reduces the amount of warning spew, just workaround the wrong warning.
llvm-svn: 105788
2010-06-10 15:06:05 +00:00
b3b9053708
Add includes to get ptrdiff_t. This is needed by gcc-4.6 which has
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done some more header trimming, resulting in cstdef being included
by less header files.
llvm-svn: 105786
2010-06-10 10:13:58 +00:00
5f2adccc1b
Teach tablegen to allow "let" expressions inside multiclasses,
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providing more ways to factor out commonality from the records.
llvm-svn: 105776
2010-06-10 02:42:59 +00:00
38f6560461
Code refactoring, no functionality changes.
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llvm-svn: 105775
2010-06-10 02:09:31 +00:00
2901371c32
Delete code that's not safe.
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llvm-svn: 105774
2010-06-10 02:08:20 +00:00
46e9dc4e6b
NEON support for _lane ops, and multiplies by scalar.
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llvm-svn: 105769
2010-06-10 00:16:56 +00:00
5fa0158ecd
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
...
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
llvm-svn: 105758
2010-06-09 22:21:24 +00:00
d53a2cb4ac
Testcase for r105741.
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llvm-svn: 105750
2010-06-09 20:30:22 +00:00
8bc5eca331
Mark physregs defined by inline asm as implicit.
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This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.
llvm-svn: 105749
2010-06-09 20:05:00 +00:00
a0746bd50a
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
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llvm-svn: 105745
2010-06-09 19:26:01 +00:00
5ac1d23d3d
It's an error to translate this:
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%reg1025 = <sext> %reg1024
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%reg1026 = SUBREG_TO_REG 0, %reg1024, 4
into this:
%reg1025 = <sext> %reg1024
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%reg1027 = EXTRACT_SUBREG %reg1025, 4
%reg1026 = SUBREG_TO_REG 0, %reg1027, 4
The problem here is that SUBREG_TO_REG is there to assert that an implicit zext
occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG
here, it will give us the value after the <sext>, not the original value of
%reg1024 before <sext>.
llvm-svn: 105741
2010-06-09 19:00:55 +00:00
ae83e1f5cb
Revert 105540, 105542, 105544, 105546, and 105548 to unbreak bootstrapping.
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llvm-svn: 105740
2010-06-09 18:59:43 +00:00
db9e260123
- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it
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is used to assert that an *implicit* zext is performed.
- Fix grammar-o in INSERT_SUBREG. (required reformatting)
llvm-svn: 105735
2010-06-09 18:15:36 +00:00
add2aa009c
Further refine types for operations which take scalars.
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This will be used primarily by NEON shift intrinsics.
llvm-svn: 105733
2010-06-09 18:02:26 +00:00
e16d569932
Workaround SCEV non-determinism on this test, for now, to get buildbots back to
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green. Dan, please revert this once the real problem is fixed.
llvm-svn: 105732
2010-06-09 17:54:40 +00:00
9f403695e1
Change another reference to the "indirect callgraph node" to
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refer to the "external node" instead.
llvm-svn: 105731
2010-06-09 17:39:05 +00:00
516473902b
Output "external node" rather than "Indirect CallGraph node" when printing
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callgraph SCC's. This makes it match what the node itself would print. Also,
"indirect callgraph node" doesn't make sense - it has nothing particularly to
do with indirect calls.
llvm-svn: 105730
2010-06-09 17:35:00 +00:00
223c481b1c
How about ULL...
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llvm-svn: 105726
2010-06-09 16:16:48 +00:00
9b21208bfb
Pulled CodeMetrics out of InlineCost.h and made it a bit more general, so it can be reused from PartialSpecializationCost
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llvm-svn: 105725
2010-06-09 15:11:37 +00:00
5e0862f7f5
Fix SPU to cope with vector insertelement to an undef position.
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We default to inserting to lane 0.
llvm-svn: 105722
2010-06-09 09:58:17 +00:00
056113a211
Handle loading from/storing to undef pointers on SPU by inserting a
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random load/store, rather than crashing llc.
llvm-svn: 105710
2010-06-09 08:29:41 +00:00
8fc7823e4d
Specialize I-Class instructions better so that we have less work to do in codegen.
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Parenthesize macro args
llvm-svn: 105682
2010-06-09 05:11:55 +00:00
83c64ee8de
Typo.
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llvm-svn: 105677
2010-06-09 03:49:12 +00:00
7c26de3b0a
Fix a gcc warning:
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'class llvm::DAGDeltaAlgorithm' has virtual functions and accessible non-virtual destructor
Not sure if this is the best solution, but this class has state and some of the
classes that inherit from it also do, so it looks appropriate.
llvm-svn: 105675
2010-06-09 03:00:05 +00:00
ab44d1281a
A few new x86-64 specific README entries.
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llvm-svn: 105674
2010-06-09 02:43:17 +00:00
47cd593023
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
...
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
llvm-svn: 105669
2010-06-09 01:46:50 +00:00
86a67bb573
Handle instructions which need to be #defines for the purpose of capturing constant arguments
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Handle extract hi/lo with common code
llvm-svn: 105666
2010-06-09 01:09:00 +00:00
a13b1c29b0
Add argument name comments.
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llvm-svn: 105665
2010-06-09 00:40:31 +00:00
0de0f3fc02
Incremental improvement to the handling of the x86 "Jump if rCX Zero"
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instruction. Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode. Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.
llvm-svn: 105661
2010-06-08 23:48:44 +00:00
6ab55c5683
Split out these asserts so it's more apparent why we're not assembling
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that rip-relative address when executing in 32-bit mode.
llvm-svn: 105656
2010-06-08 22:57:33 +00:00
8fe3cc8055
fix copy/paste/modify think-o
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llvm-svn: 105653
2010-06-08 22:53:32 +00:00
c2f87b7bb2
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
llvm-svn: 105652
2010-06-08 22:51:23 +00:00
89d103a8ce
Ensure that mov and not lea are used to stick the address into
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the register. While we're at it, make sure it's in the right one.
llvm-svn: 105645
2010-06-08 22:04:25 +00:00
281d6bc894
Makefiles: Teach LLVM's recursive makefile descent to update objdir Makefiles if
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they are out of date, instead of only testing if they exist.
llvm-svn: 105636
2010-06-08 20:10:13 +00:00
57c6fd452e
fix typo
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llvm-svn: 105634
2010-06-08 20:06:55 +00:00
5729f51410
Use const_iterator where appropriate.
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llvm-svn: 105620
2010-06-08 17:21:57 +00:00
f2363de7ad
DeltaAlgorithm: Tweak split to split by first/second half instead of even/odd, since adjacent changes are more likely to be related.
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llvm-svn: 105613
2010-06-08 16:21:26 +00:00
579ba2ac42
ADT: Add DAGDeltaAlgorithm, which is a DAG minimization algorithm built on top of the standard 'delta debugging' algorithm.
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- This can give substantial speedups in the delta process for inputs we can construct dependency information for.
llvm-svn: 105612
2010-06-08 16:21:22 +00:00
efac7f5e90
Add more virtual memory to lit. The python in x86-64 fedora 13 needs it to run
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the llvm tests :-(
It was failing with
-- Testing: 5324 tests, 8 threads --
Fatal Python error: PyEval_AcquireThread: NULL new thread state
llvm-svn: 105610
2010-06-08 16:17:58 +00:00
4e36e5bb4c
Use realloc instead of malloc+memcpy when growing a POD SmallVector. A smart
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realloc implementation can try to expand the allocated memory block in-place,
avoiding the copy.
llvm-svn: 105605
2010-06-08 11:44:30 +00:00
6c40caf729
Flag SPU's function call sequence together.
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Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html
llvm-svn: 105601
2010-06-08 07:55:16 +00:00
d80ce4f861
Fix a valgrind error.
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llvm-svn: 105600
2010-06-08 07:11:17 +00:00
8615667bac
Refine BuiltinsARM.def types a bit, we should do a better job of this to save some c++ code in CGBuiltins.
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llvm-svn: 105598
2010-06-08 06:01:16 +00:00
0271c5928e
Fix up a comment.
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llvm-svn: 105591
2010-06-08 00:42:08 +00:00
fe123268a9
ARM NEON:
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fix vcvt naming
handle vdup, vcombine with generic vector code
llvm-svn: 105588
2010-06-08 00:14:42 +00:00
846bd7992c
Further changes for Neon vector shuffles:
...
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
llvm-svn: 105586
2010-06-07 23:53:38 +00:00
7149cfcda3
Fix a mistake in my previous change r105437: don't access operand 2 and assume
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that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.
llvm-svn: 105585
2010-06-07 23:48:46 +00:00
7398758719
Add some basic debug output.
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llvm-svn: 105561
2010-06-07 22:32:10 +00:00
8612940357
Tweak test for debug/metadata change, update to FileCheck. Radar 7424645.
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llvm-svn: 105559
2010-06-07 21:50:54 +00:00
723d242a95
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
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rdar://7797940
llvm-svn: 105557
2010-06-07 21:48:47 +00:00
4ecf2cc5ea
Plug a leak in the non-error case by removing one level of indirection.
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llvm-svn: 105556
2010-06-07 21:42:19 +00:00
6201b991a2
Cleanup. Process the dbg_values separately
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llvm-svn: 105554
2010-06-07 21:28:55 +00:00
22e1adbb11
Fix this test to work under lit.
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llvm-svn: 105553
2010-06-07 20:58:11 +00:00
fa9ad13002
Run dead type elimination after dead argument elimination.
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llvm-svn: 105552
2010-06-07 20:28:37 +00:00
fb8ed43349
Make bugpoint dead-argument-hacking actually work, and actually test it.
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llvm-svn: 105551
2010-06-07 20:20:33 +00:00
34a2249fde
Use ->isVoidTy().
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llvm-svn: 105550
2010-06-07 20:19:26 +00:00
ebf2e977cf
The FoldingSet hash data includes pointer values, so it isn't
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determinstic. Instead, give SCEV objects an arbitrary sequence
number.
llvm-svn: 105548
2010-06-07 19:36:14 +00:00
3553feed79
Optimize this code somewhat by taking advantage of the fact
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that the operands are sorted.
llvm-svn: 105546
2010-06-07 19:20:57 +00:00
cfcd0e12cf
Another place where the code wanted to access the argument list and not all of
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the operands.
llvm-svn: 105545
2010-06-07 19:18:58 +00:00
a2effb6452
Micro-optimize this, to speed up this hotspot in debug builds a little.
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llvm-svn: 105544
2010-06-07 19:16:37 +00:00
18a4b46404
Micro-optimize this.
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llvm-svn: 105542
2010-06-07 19:12:54 +00:00
0f445f328e
Move exit check where it really belongs.
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llvm-svn: 105541
2010-06-07 19:12:21 +00:00
70910a6ab6
Optimize ScalarEvolution's SCEVComplexityCompare predicate: don't go
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scrounging through SCEVUnknown contents and SCEVNAryExpr operands;
instead just do a simple deterministic comparison of the precomputed
hash data.
Also, since this is more precise, it eliminates the need for the slow
N^2 duplicate detection code.
llvm-svn: 105540
2010-06-07 19:06:13 +00:00
a3bba3371a
Create new accessors to get arguments for call/invoke instructions. It breaks
...
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.
llvm-svn: 105539
2010-06-07 19:05:06 +00:00
c4dca3aeb6
Misc cleanups to the gold plugin.
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llvm-svn: 105534
2010-06-07 16:45:22 +00:00
12d1f62f6c
clang codegen support
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llvm-svn: 105531
2010-06-07 16:00:37 +00:00
1850444000
Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization. Patch by Takumi Nakamura\!
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llvm-svn: 105528
2010-06-05 14:50:21 +00:00
e4f45cc88f
This bug is also present in MSVC10. Requested by Elrood on IRC.
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llvm-svn: 105527
2010-06-05 12:40:43 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
...
yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
c4f614870f
Teach tablegen to support 'defm' inside multiclasses.
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llvm-svn: 105519
2010-06-05 02:11:52 +00:00
0501b03242
Make MachineFunctionPass::createPrinterPass private, as no subclasses
...
should be calling it.
llvm-svn: 105517
2010-06-05 01:19:12 +00:00
81ef35b3ca
Improvements to tail call code. No functional effect
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unless using -arm-tail-calls.
llvm-svn: 105515
2010-06-05 00:51:39 +00:00
520913cf9e
getFoldedOffsetOf no longer does anything special with vector types.
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llvm-svn: 105514
2010-06-05 00:47:34 +00:00
8c292adba4
No need to special-case structs here; structs are first-class now.
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llvm-svn: 105513
2010-06-05 00:42:29 +00:00
3ca391027f
Revert 105492 & 105493 due to a testcase regression. Radar 7424645.
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llvm-svn: 105511
2010-06-05 00:39:29 +00:00
bbfb6aca92
LSR needs to remember inserted instructions even in postinc mode, because
...
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.
llvm-svn: 105510
2010-06-05 00:33:07 +00:00
df1a7f83bf
Fix some liveout handling related to tail calls, see comments.
...
I don't think this ever resulted in problems on x86, but it
would on ARM.
llvm-svn: 105509
2010-06-05 00:30:45 +00:00
d7910a805d
Implement operator== and operator!= for SetVector.
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llvm-svn: 105508
2010-06-05 00:26:02 +00:00
3eed2cf587
test case for r105504.
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Radar 8055687.
llvm-svn: 105505
2010-06-04 23:47:41 +00:00
Alexis Hunt