Commit Graph

6 Commits

Author SHA1 Message Date
Andrew Trick 10ffc2b6c2 Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541
2010-12-24 05:03:26 +00:00
Chris Lattner af29ea6d57 eliminate the last DOUTs from the targets.
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
Dan Gohman 7e105f0b12 Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.

llvm-svn: 62284
2009-01-15 22:18:12 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Scott Michel d1b5b9f68c Updated source file headers to llvm coding standard.
llvm-svn: 44597
2007-12-05 01:40:25 +00:00
Scott Michel 6e22c651d1 More of the Cell SPU code drop from "Team Aerospace".
llvm-svn: 44582
2007-12-04 22:23:35 +00:00