080d86fecc
Reindent.
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llvm-svn: 117538
2010-10-28 08:25:44 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
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- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
523fa3a2e8
Fix a major bug in operand latency computation. The use index must be adjusted
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by the number of defs first for it to match the instruction itinerary.
llvm-svn: 117518
2010-10-28 01:46:29 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
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Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
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llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
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llvm-svn: 117512
2010-10-27 23:56:39 +00:00
6c55007edb
Fix compiler warnings about signed/unsigned comparisons.
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llvm-svn: 117511
2010-10-27 23:49:00 +00:00
16bb87a90e
Teach InstCombine not to use Add and Neg on FP. PR 8490.
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llvm-svn: 117510
2010-10-27 23:45:18 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
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complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
cbdf7e874a
Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.
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llvm-svn: 117506
2010-10-27 23:17:17 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
055de2c789
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
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llvm-svn: 117495
2010-10-27 21:28:09 +00:00
f8537165bd
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.
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llvm-svn: 117494
2010-10-27 21:23:52 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
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llvm-svn: 117485
2010-10-27 20:46:49 +00:00
f4ea7084c5
JIT imm12 encoding for constant pool entry references.
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llvm-svn: 117483
2010-10-27 20:39:40 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
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elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
24c8b04d5f
Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.
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llvm-svn: 117481
2010-10-27 20:28:07 +00:00
333b0a9e74
ARM JIT fix for LDRi12 and company.
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llvm-svn: 117478
2010-10-27 19:55:59 +00:00
14807270be
Replace pointer arithmetic with StringRef::substr.
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llvm-svn: 117477
2010-10-27 19:53:52 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
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llvm-svn: 117475
2010-10-27 19:25:54 +00:00
7db918f1e9
x86-Win32: Switch ftol2 calling convention from stdcall to C.
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llvm-svn: 117474
2010-10-27 18:52:38 +00:00
0f83d96852
COFF: Add IMAGE_SCN_MEM_READ to text sections.
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There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.
llvm-svn: 117473
2010-10-27 18:52:29 +00:00
fbdab0d633
Fix whitespace.
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llvm-svn: 117472
2010-10-27 18:52:20 +00:00
095fa9e5cc
Set default type and flags for .init and .fini.
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llvm-svn: 117471
2010-10-27 18:45:20 +00:00
26496e6835
Produce an error for an invalid use of .symver.
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llvm-svn: 117462
2010-10-27 17:56:18 +00:00
ba1c6cd62f
The new LDR* instruction patterns should handle the necessary encoding of
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operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
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llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
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llvm-svn: 117458
2010-10-27 17:29:29 +00:00
8bf1483a3d
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
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encoding tricks. Handle the 'imm doesn't fit in the insn' case.
llvm-svn: 117454
2010-10-27 16:50:31 +00:00
e4992c88a4
Formatting.
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llvm-svn: 117453
2010-10-27 16:30:18 +00:00
cc1b168ef6
Symbols defined as the difference of other two end up in the ABS section.
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llvm-svn: 117451
2010-10-27 16:04:30 +00:00
eb0c2c170d
Add support for the .symver directive. This is really ugly, but most of it is
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contained in the ELF object writer.
llvm-svn: 117448
2010-10-27 15:18:17 +00:00
a5efd6a27c
Move more logic to isInSymtab and simplify.
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llvm-svn: 117447
2010-10-27 14:44:52 +00:00
258b8e1dc8
80-col violation.
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llvm-svn: 117443
2010-10-27 09:09:10 +00:00
32acd741d2
Remove try/catch(...) from Win32/Signals.inc.
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catch(...) is used in Win32/Signals.inc for catching Win32 structured
exceptions, but according to [1], this is wrong.
We can't simply change try/catch to __try/__finally, since this syntax is not
supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1
macros on MinGW [2], but I think that that solution obfuscates the code too
much.
The use of try/catch(...) in Signals.inc makes it impossible to link
MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we
just remove try/catch(...) from Signals.inc, since the meaning of the code won't
change.
[1] http://members.cox.net/doug_web/eh.htm
[2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315
llvm-svn: 117442
2010-10-27 09:09:04 +00:00
9ad2166899
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
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(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
20b021c970
Another tweak to X86 instructions to add the missing flex instruction (without
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the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
a1917c7555
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
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sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
9d2d1f0f00
LDRi12 machine instructions handle negative offset operands normally (simple
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integer values), not with the addrmode2 encoding.
llvm-svn: 117429
2010-10-27 01:19:41 +00:00
ba985d9dd5
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
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will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
79e1407c11
Handle critical loop predecessors by making both inside and outside registers
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live out.
This doesn't prevent us from inserting a loop preheader later on, if that is
better.
llvm-svn: 117424
2010-10-27 00:39:07 +00:00
795ed98180
Compute critical loop predecessors in the same way as critical loop exits.
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Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.
llvm-svn: 117423
2010-10-27 00:39:05 +00:00
0e7a011a00
Physical registers trivially have multiple connected components all the time.
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Only virtuals should be requires to be connected.
llvm-svn: 117422
2010-10-27 00:39:01 +00:00
2577b2e8b1
One more spot where the new arm mode LDR instruction representation
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doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
e9b429e96f
Adding disassembler to the MicroBlaze backend.
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llvm-svn: 117420
2010-10-27 00:23:01 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
Mikhail Glushenkov