Commit Graph

96560 Commits

Author SHA1 Message Date
Bernard Ogden 4400cde89a Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

llvm-svn: 192590
2013-10-14 13:16:57 +00:00
Matheus Almeida 2102188cfc [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
2013-10-14 13:07:39 +00:00
Matheus Almeida 5be0cd8720 [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
2013-10-14 12:57:18 +00:00
Matheus Almeida 7d65ea76ea [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
llvm-svn: 192587
2013-10-14 12:38:17 +00:00
Matheus Almeida bc189eb318 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
2013-10-14 12:22:43 +00:00
Matheus Almeida b74293dc55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
2013-10-14 11:49:30 +00:00
Evgeniy Stepanov 9b5517b127 [msan] Fix handling of scalar select of vectors.
llvm-svn: 192575
2013-10-14 09:52:09 +00:00
Elena Demikhovsky 82a46ebe0a Fixed a bug in dynamic allocation memory on stack.
The alignment of allocated space was wrong, see Bugzila 17345.

Done by Zvi Rackover <zvi.rackover@intel.com>.

llvm-svn: 192573
2013-10-14 07:26:51 +00:00
Craig Topper d7abdb6f12 Create classes to reduce the size of the tablegen entries for the CRC32 instructions.
llvm-svn: 192568
2013-10-14 05:19:58 +00:00
Craig Topper a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
Craig Topper 4432208884 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
llvm-svn: 192566
2013-10-14 01:42:32 +00:00
Craig Topper 7158745e55 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
llvm-svn: 192565
2013-10-14 01:21:22 +00:00
David Majnemer 93fdc3fabf Windows: Fix a typo in an assert
llvm-svn: 192564
2013-10-14 01:17:32 +00:00
Craig Topper c4a5a3f65d Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions.
llvm-svn: 192562
2013-10-14 00:24:33 +00:00
David Majnemer 7af18578f8 Windows: Don't bother with pinning Kernel32.dll
We don't delay load it so it shouldn't be going anywhere.

llvm-svn: 192561
2013-10-14 00:06:58 +00:00
Will Dietz 5357df6290 MC: Don't assume incoming StringRef's are null terminated.
This can happen when processing command line arguments, which
are often stored as std::string's and later turned into
StringRef's via std::string::data().  Unfortunately this
is not guaranteed to return a null-terminated string
until C++11, causing breakage on platforms that don't do this.

llvm-svn: 192558
2013-10-13 22:09:26 +00:00
Vincent Lejeune d6cbede9c5 R600: improve dump of S_WAITCNT
llvm-svn: 192557
2013-10-13 17:56:28 +00:00
Vincent Lejeune 4ee6dd6136 R600/SI: Add SinkingPass before ISel
llvm-svn: 192556
2013-10-13 17:56:21 +00:00
Vincent Lejeune d623644d17 R600/SI: Support byval arguments
llvm-svn: 192555
2013-10-13 17:56:16 +00:00
Vincent Lejeune fa58a5fb60 R600: Use masked read sel for texture instructions
llvm-svn: 192554
2013-10-13 17:56:10 +00:00
Vincent Lejeune 301beb80d4 R600: fix swizzle export
llvm-svn: 192553
2013-10-13 17:56:04 +00:00
Vincent Lejeune 533352f696 R600: Clear the VPM bit of export instructions.
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552
2013-10-13 17:55:57 +00:00
David Majnemer a5732844a6 Windows: Use GetModuleHandleEx instead of LoadLibrary
We were using an anti-pattern of:
 - LoadLibrary
 - GetProcAddress
 - FreeLibrary

This is problematic because of several reasons:
 - We are holding on to pointers into a library we just unloaded.
 - Calling LoadLibrary results in an increase in the reference count of
   the library in question and any libraries that it depends on and
   so-on and so-forth.  This is none too quick.

Instead, use GetModuleHandleEx with GET_MODULE_HANDLE_EX_FLAG_PIN.  This
is done because because we didn't bring the reference for the library
into existence and therefor shouldn't count on it being around later.

llvm-svn: 192550
2013-10-13 10:34:21 +00:00
Will Dietz ae726a93e3 TargetLowering: Don't index into empty string.
(This is triggered by current lit tests)

llvm-svn: 192549
2013-10-13 03:08:49 +00:00
Will Dietz 0b48c738e6 yaml2coff/elf: Touchup for compatibility.
* std::string::append(int, int) can be ambiguous.
* std::vector<>::data() is a C++11 feature, use ArrayRef abstraction.

llvm-svn: 192542
2013-10-12 21:29:16 +00:00
Arnold Schwaighofer 58864d2d5f SLPVectorizer: Sort PHINodes based on their opcode
Before this patch we relied on the order of phi nodes when we looked for phi
nodes of the same type. This could prevent vectorization of cases where there
was a phi node of a second type in between phi nodes of some type.

This is important for vectorization of an internal graphics kernel. On the test
suite + external on x86_64 (and on a run on armv7s) it showed no impact on
either performance or compile time.

radar://15024459

llvm-svn: 192537
2013-10-12 18:56:27 +00:00
Tobias Grosser 5cff1e2d78 LoopVectorize: Add missing INITIALIZE_PASS_DEPENDENCY macros
Contributed-by:  Peter Zotov  <whitequark@whitequark.org>
llvm-svn: 192536
2013-10-12 18:29:15 +00:00
Benjamin Kramer f016258068 Force a CPU on test so it doesn't depend on microarchitectural scheduling decisions.
llvm-svn: 192532
2013-10-12 11:17:12 +00:00
Bill Wendling 58463e4e83 Update so that it uses the `-V' command line option and supports Python 3.x.
llvm-svn: 192527
2013-10-12 08:42:59 +00:00
Craig Topper 88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
llvm-svn: 192525
2013-10-12 05:41:08 +00:00
Tom Stellard ed69925998 R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523
2013-10-12 05:02:51 +00:00
Craig Topper aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
Reed Kotler de64774b4d For Mips16, start to consolidate all forms of 32 bit literal loading so that
they can be better handled and optimized in the Mips16 constant island code.

llvm-svn: 192520
2013-10-12 02:19:08 +00:00
Will Dietz 981af0021b Add missing #include's to cctype when using isdigit/alpha/etc.
llvm-svn: 192519
2013-10-12 00:55:57 +00:00
Manman Ren 4c4b69c9c8 Debug Info: remove form from function addDIEEntry.
The form must be a reference form in addDIEEntry. Which reference form to
use will be decided by the callee.

No functionality change.

llvm-svn: 192517
2013-10-11 23:58:05 +00:00
Andrew Kaylor 6587bcfdbc Fixing problems in lli's RemoteMemoryManager.
This fixes a problem from a previous check-in where a return value was omitted.

Previously the remote/stubs-remote.ll and remote/stubs-sm-pic.ll tests were reporting passes, but they should have been failing.  Those tests attempt to link against an external symbol and remote symbol resolution is not supported.  The old RemoteMemoryManager implementation resulted in local symbols being used for resolution and the child process crashed but the test didn't notice.  With this check-in remote symbol resolution fails, and so the test (correctly) fails.

llvm-svn: 192514
2013-10-11 22:47:10 +00:00
Andrew Kaylor 7bb1344c67 Adding multiple object support to MCJIT EH frame handling
llvm-svn: 192504
2013-10-11 21:25:48 +00:00
Matt Arsenault 441387832e R600: Add scalar i32 add test
llvm-svn: 192501
2013-10-11 21:03:41 +00:00
Matt Arsenault c15b85715e Use CHECK-LABEL
llvm-svn: 192500
2013-10-11 21:03:39 +00:00
Matt Arsenault 8fb373891f Fix typo
llvm-svn: 192499
2013-10-11 21:03:36 +00:00
Benjamin Kramer a9767aed80 fConversion: Attempt #2 at fixing the MSVC build.
llvm-svn: 192492
2013-10-11 19:49:09 +00:00
Benjamin Kramer 24906d9697 IfConversion: Try to unbreak the MSVC build.
llvm-svn: 192487
2013-10-11 19:39:48 +00:00
Benjamin Kramer 8a37f63714 Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
2013-10-11 19:05:08 +00:00
Matthias Braun d616ccc069 Remove kill flags after if conversion if necessary
When if converting something like:
true:
   ... = R0<kill>

false:
   ... = R0<kill>

then the instructions of the true block must not have a <kill> flag
anymore, as the instruction of the false block follow and do still read
the R0 value.
Specifically this patch determines the set of register live-in in the
false block (possibly after simulating the liveness changes of the
duplicated instructions). Each of these live-in registers mustn't be
killed.

llvm-svn: 192482
2013-10-11 19:04:37 +00:00
Matthias Braun 5bfee00dfa Introduce ad hoc liveness tracking utility: LiveRegUnits
Contains a set of live register (units) and code to move forward and
backward in the schedule while updating the live set.

llvm-svn: 192481
2013-10-11 19:04:35 +00:00
Quentin Colombet c50b943b31 [DAGCombiner] Load slicing test case: attempt to really fix the buildbots (used sse4.2 instead of avx!).
<rdar://problem/14477220>

llvm-svn: 192480
2013-10-11 18:54:49 +00:00
Renato Golin 58ab84a830 Add warning about CHECK-DAG with variable definition
llvm-svn: 192479
2013-10-11 18:50:22 +00:00
Manman Ren 1848cb6654 Debug Info Testing Case: check for the name of a structure.
llvm-svn: 192478
2013-10-11 18:50:00 +00:00
Stephen Lin e93a3a088f Really fix CHECK-LABEL and CHECK-DAG interaction. This actually just restores the initial implementation that was in r186162 but got lost in some subsequent refactoring. More explicit variable names and comments are present now to hopefully prevent repeat regression, as well as another test.
llvm-svn: 192477
2013-10-11 18:38:36 +00:00
Quentin Colombet de0e06234c [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support.
This should fix the buildbots.

Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32

into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>

llvm-svn: 192476
2013-10-11 18:29:42 +00:00