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43 Commits

Author SHA1 Message Date
Evan Cheng 40921a4e62 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Evan Cheng 49e02fc414 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786
 2010-08-11 06:30:38 +00:00
Evan Cheng 6e809de90c - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Evan Cheng ce8fb68078 Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations. 
llvm-svn: 110584
 2010-08-09 18:35:19 +00:00
Evan Cheng 58066e337d Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). 
llvm-svn: 108256
 2010-07-13 19:21:50 +00:00
Jim Grosbach 151cd8f159 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach 92d999001c Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Anton Korobeynikov 15ccae2a46 Some bits of A9 scheduling: VFP 
llvm-svn: 100643
 2010-04-07 18:19:18 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. 
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
 2010-04-05 03:10:20 +00:00
Jim Grosbach 7c90d22f4c vml[as] are slow on 1136jf-s also. 
llvm-svn: 100066
 2010-04-01 00:13:43 +00:00
Jim Grosbach 71fcb4fedd switch the flag for using NEON for SP floating point to a subtarget 'feature'. 
Re-commit. This time complete with testsuite updates.

llvm-svn: 99570
 2010-03-25 23:47:34 +00:00
Jim Grosbach 42bb89c7d9 need to fix 'make check' tests first. revert for a moment. 
llvm-svn: 99569
 2010-03-25 23:34:05 +00:00
Jim Grosbach 7fce4e39aa switch the flag for using NEON for SP floating point to a subtarget 'feature' 
llvm-svn: 99568
 2010-03-25 23:32:19 +00:00
Jim Grosbach a43386ba8f switch the use-vml[as] instructions flag to a subtarget 'feature' 
llvm-svn: 99565
 2010-03-25 23:11:16 +00:00
Anton Korobeynikov 0a65a37344 Add substarget feature for FP16 
llvm-svn: 98503
 2010-03-14 18:42:38 +00:00
David Goodwin 1fd5fdaa7b Add ARMv6 itineraries. 
llvm-svn: 89218
 2009-11-18 18:39:57 +00:00
Anton Korobeynikov 14635da94b Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
llvm-svn: 85764
 2009-11-02 00:10:38 +00:00
David Goodwin 1cc6dd97da Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
llvm-svn: 83218
 2009-10-01 22:19:57 +00:00
David Goodwin 9a051a5922 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
llvm-svn: 83215
 2009-10-01 21:46:35 +00:00
David Goodwin 17199b56b0 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
llvm-svn: 83122
 2009-09-30 00:10:16 +00:00
David Goodwin afcaf79603 Checkpoint NEON scheduling itineraries. 
llvm-svn: 82657
 2009-09-23 21:38:08 +00:00
David Goodwin fd5defed1d Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
llvm-svn: 78736
 2009-08-11 22:38:43 +00:00
David Goodwin 742db6a6d4 Make NEON single-precision FP support the default for cortex-a8 (again). 
llvm-svn: 78430
 2009-08-07 23:32:33 +00:00
David Goodwin 21788bef7c Disable NEON single-precision FP support for Cortex-A8, for now... 
llvm-svn: 78209
 2009-08-05 16:40:57 +00:00
David Goodwin a307edbdd5 By default, for cortex-a8 use NEON for single-precision FP. 
llvm-svn: 78200
 2009-08-05 16:01:19 +00:00
David Goodwin 3b9c52c5c1 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng 18e32946f8 Add fake v7 itineraries for now. 
llvm-svn: 76612
 2009-07-21 18:54:14 +00:00
Evan Cheng 14965760a7 Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant. 
llvm-svn: 74988
 2009-07-08 01:46:35 +00:00
Evan Cheng 4e712de541 Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
llvm-svn: 73747
 2009-06-19 01:51:50 +00:00
Anton Korobeynikov c82b282b34 Separate V6 from V6T2 since the latter has some extra nice instructions 
llvm-svn: 73085
 2009-06-08 21:20:36 +00:00
Anton Korobeynikov b6f4538683 Add placeholder for thumb2 stuff 
llvm-svn: 72593
 2009-05-29 23:41:08 +00:00
Anton Korobeynikov 0b91cc4260 Add ARMv7 architecture, Cortex processors and different FPU modes handling. 
llvm-svn: 72337
 2009-05-23 19:51:43 +00:00
Bob Wilson a4c2290e5f Use CallConvLower.h and TableGen descriptions of the calling conventions 
for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371
 2009-04-17 19:07:39 +00:00
Evan Cheng 977e7be9d4 Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. 
llvm-svn: 59953
 2008-11-24 07:34:46 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Lauro Ramos Venancio 8f8199086f Add a processor. 
llvm-svn: 36765
 2007-05-04 22:16:30 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Evan Cheng 305c49579c getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 
llvm-svn: 28378
 2006-05-18 00:12:58 +00:00
Evan Cheng dcec882286 Remove PointerType from class Target 
llvm-svn: 28368
 2006-05-17 21:20:27 +00:00
Rafael Espindola ffdc24b847 added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00