replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
30,927 Commits 2 Branches 0 Tags 1.8 GiB
Commit Graph

30927 Commits

Author SHA1 Message Date
Reid Spencer 49bd921f08 Add and Operator== method to ValID so equality can be done properly for 
named or numbered ValIDs.

llvm-svn: 35172
 2007-03-19 18:34:28 +00:00
Reid Spencer 508167861d For PR1258: 
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.

llvm-svn: 35171
 2007-03-19 18:32:53 +00:00
Reid Spencer 7953b683fc For PR1258: 
Revise numeric value references to accommodate collapsed type planes.

llvm-svn: 35170
 2007-03-19 18:27:35 +00:00
Chris Lattner 9c62db7c8c fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll 
llvm-svn: 35169
 2007-03-19 18:25:57 +00:00
Reid Spencer 175296cd1b Use opt instead of gccas. 
llvm-svn: 35168
 2007-03-19 18:25:55 +00:00
Chris Lattner 50fce05a21 add a testcase the resent patches fail on. 
llvm-svn: 35167
 2007-03-19 18:25:48 +00:00
Reid Spencer 104b47041a Don't upgrade these. 
llvm-svn: 35166
 2007-03-19 18:08:42 +00:00
Evan Cheng 25d00d545d Remove -reduce-joining-phys-regs options. Make it on by default. 
llvm-svn: 35165
 2007-03-19 18:08:26 +00:00
Duncan Sands 5a040c510b Fix obvious typo in comment. 
llvm-svn: 35164
 2007-03-19 14:25:02 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng 5be3e09a30 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng 461c964d3d Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Evan Cheng 9d7d130835 Recognize target instruction flag 'isReMaterializable'. 
llvm-svn: 35159
 2007-03-19 06:20:37 +00:00
Evan Cheng 0420161130 Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable". 
It means the instruction can be easily re-materialized at any point. e.g.
constant generation, load from constantpool.

llvm-svn: 35158
 2007-03-19 06:19:16 +00:00
Zhou Sheng f89ea5068f Add isStrictPositive() to APInt to determine if this APInt Value > 0. 
llvm-svn: 35156
 2007-03-19 05:22:18 +00:00
Evan Cheng c5e74f6404 Minor bug fix. 
llvm-svn: 35153
 2007-03-19 04:22:35 +00:00
Chris Lattner f01f87bc63 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner 23dd31a3af add PR# 
llvm-svn: 35151
 2007-03-19 00:17:19 +00:00
Chris Lattner 877a3b424d implement the next chunk of SROA with memset/memcpy's of aggregates. This 
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

llvm-svn: 35150
 2007-03-19 00:16:43 +00:00
Chris Lattner dcd44dbbb0 add pr# 
llvm-svn: 35149
 2007-03-19 00:15:43 +00:00
Chris Lattner ee3c5d1b78 new testcase 
llvm-svn: 35148
 2007-03-19 00:11:30 +00:00
Chris Lattner 2c0f36bc39 testcase for SROA with memset etc 
llvm-svn: 35147
 2007-03-19 00:09:00 +00:00
Nick Lewycky db204ecfbc Clean up this code and fix subtract miscompile. 
llvm-svn: 35146
 2007-03-18 22:58:46 +00:00
Chris Lattner 0741842b3b Implement InstCombine/and-xor-merge.ll:test[12]. 
Rearrange some code to simplify it now that shifts are binops

llvm-svn: 35145
 2007-03-18 22:51:34 +00:00
Chris Lattner 1ada0693ab new testcase 
llvm-svn: 35144
 2007-03-18 22:50:57 +00:00
Chris Lattner 9b3e2b4ad9 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky f764441977 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Evan Cheng d8f2e4fe4c - Merge UsedBlocks info after two virtual registers are coalesced. 
- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141
 2007-03-18 09:05:55 +00:00
Evan Cheng 5382426577 Keep UsedBlocks info accurate. 
llvm-svn: 35140
 2007-03-18 09:02:31 +00:00
Evan Cheng fd43be8532 Fix comment. 
llvm-svn: 35139
 2007-03-18 03:26:04 +00:00
Nick Lewycky 17d20fd41e Propagate ValueRanges across equality. 
Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138
 2007-03-18 01:09:32 +00:00
Anton Korobeynikov 22f436da42 Silence warning 
llvm-svn: 35137
 2007-03-17 14:48:06 +00:00
Evan Cheng f6f043332f Track the BB's where each virtual register is used. 
llvm-svn: 35135
 2007-03-17 09:29:54 +00:00
Evan Cheng 7b2a001669 Joining a live interval of a physical register with a virtual one can turn out 
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134
 2007-03-17 09:27:35 +00:00
Evan Cheng a2465dfc07 Use SmallSet instead of std::set. 
llvm-svn: 35133
 2007-03-17 08:53:30 +00:00
Evan Cheng be22235790 If sdisel has decided to sink GEP index expression into any BB. Replace all uses 
in that BB.

llvm-svn: 35132
 2007-03-17 08:22:49 +00:00
Evan Cheng bbe11722e2 GEP index sink test case. 
llvm-svn: 35131
 2007-03-17 03:18:32 +00:00
Devang Patel ac1f488548 Test case for X86 inline asm constraint 'I' 
llvm-svn: 35130
 2007-03-17 00:14:52 +00:00
Devang Patel b38c2ec89c Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio 25d4052af6 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng c5bc763f50 Turn on GEP index sinking by default. 
llvm-svn: 35127
 2007-03-16 18:32:30 +00:00
Evan Cheng 0a9d0cabaf Stupid bug. 
llvm-svn: 35126
 2007-03-16 17:50:20 +00:00
Bill Wendling 144b8bbf17 And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng 009ea54262 Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
 2007-03-16 08:46:27 +00:00
Evan Cheng 0e34d6af6b Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng a2a2fd1e55 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.

llvm-svn: 35121
 2007-03-16 08:42:32 +00:00
Evan Cheng 2ae53613ca These forward declarations are not needed. 
llvm-svn: 35120
 2007-03-16 08:41:06 +00:00
Nick Lewycky 4f73de2b4e Add more comments and update to new asm syntax. 
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119
 2007-03-16 02:37:39 +00:00
Bill Wendling e31034125c Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00