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Author SHA1 Message Date
Bruno Cardoso Lopes 0a17241a0d Shrink down SSE3 code by some multiclass refactoring - 1st part 
llvm-svn: 107438
 2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes 5e88700f28 Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes 886ee33a38 Add AVX SSE3 packed addsub instructions 
llvm-svn: 107404
 2010-07-01 17:08:18 +00:00
Dan Gohman 722f5fc567 Enable on-demand fast-isel. 
llvm-svn: 107377
 2010-07-01 02:58:57 +00:00
Dan Gohman 207624edb0 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.

llvm-svn: 107376
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes a7a0c83563 Add AVX SSE3 replicate and convert instructions 
llvm-svn: 107375
 2010-07-01 02:33:39 +00:00
Dan Gohman 7937d5606d Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.

llvm-svn: 107373
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes 05166740eb - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes d0eacf715f Move MOVD/MODQ code around, creating sections for each of them 
llvm-svn: 107308
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes cbcebe2950 Add AVX SSE2 mask creation and conditional store instructions 
llvm-svn: 107306
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes 5c768e4915 Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
llvm-svn: 107300
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes d079c91683 Add AVX SSE2 packed integer extract/insert instructions 
llvm-svn: 107293
 2010-06-30 17:03:03 +00:00
Gabor Greif 12ca3d9fac use ArgOperand API 
llvm-svn: 107280
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes e82689fea2 Add AVX SSE2 integer unpack instructions 
llvm-svn: 107246
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes ec0115c9b7 Add AVX SSE2 packed integer shuffle instructions 
llvm-svn: 107245
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes 51ceead19c Small refactoring of SSE2 packed integer shuffle instructions 
llvm-svn: 107243
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes be792feb8b Add AVX SSE2 pack with saturation integer instructions 
llvm-svn: 107241
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes 2686ea4555 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes 2e2caefff9 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes 3f71ddfaad Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes 7fee95a38e Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
llvm-svn: 107211
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes ba21eb8054 Add AVX Move Aligned/Unaligned packed integers 
llvm-svn: 107206
 2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes 30689a3a7f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes a4575f5b31 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes 049f4ffab1 Move non-temporal movs to their own section 
llvm-svn: 107168
 2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes 21a9433e9e Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Duncan Sands 67bfa9d109 Remove pointless and unused variables. 
llvm-svn: 107130
 2010-06-29 12:48:49 +00:00
Bruno Cardoso Lopes de736a6494 Refactoring of arithmetic instruction classes with unary operator 
llvm-svn: 107116
 2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes d6a091a4d4 Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bill Wendling 0a5bb081cc Reduce indentation via early exit. NFC. 
llvm-svn: 107067
 2010-06-28 21:08:32 +00:00
Gabor Greif 83205af3fa use ArgOperand API 
llvm-svn: 106944
 2010-06-26 11:51:52 +00:00
Jakob Stoklund Olesen d7d0d4e882 When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

llvm-svn: 106934
 2010-06-26 00:39:23 +00:00
Bruno Cardoso Lopes 74d716b9cd Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes 83651094ad Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes 4530fed87e revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes a34d9b6d84 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Dale Johannesen ce97d55ad9 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893
 2010-06-25 21:55:36 +00:00
Dan Gohman 8de1fe3ccf pcmpeqd and friends are Commutable. 
llvm-svn: 106886
 2010-06-25 21:05:35 +00:00
Bill Wendling e41e40f689 - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.

llvm-svn: 106880
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes 553fafc6ce Move the last piece of SSE2 convert instructions to the Convert Instructions section 
llvm-svn: 106877
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes 62d1403a03 More SSE refactoring, this time with different types of MOVs 
llvm-svn: 106876
 2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes e76c0b13b9 Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
llvm-svn: 106867
 2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes cbdcce6478 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes 447735aa98 Refactoring of SSE convert intrinsics 
llvm-svn: 106808
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes 78827d1952 Refactoring of SSE conversion instructions 
llvm-svn: 106804
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes 6b6b605917 Refactor SSE cmp intrinsics and declare the same for AVX 
llvm-svn: 106796
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes 4398fd7b83 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Dale Johannesen 5ad5226c58 Disallow matching "i" constraint to symbol addresses when 
address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.

llvm-svn: 106779
 2010-06-24 20:14:51 +00:00
Dan Gohman 600f62b3ba Reapply r106634, now that the bug it exposed is fixed. 
llvm-svn: 106746
 2010-06-24 14:30:44 +00:00
Chris Lattner 8048662539 Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734

llvm-svn: 106725
 2010-06-24 07:29:18 +00:00