210975cfbb
Handle any_extend like zext
...
llvm-svn: 23202
2005-09-02 00:16:09 +00:00
2493f0e5fd
Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on
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the observation that it only has to handle i1 -> i64 and i64 -> i1.
llvm-svn: 23201
2005-09-02 00:15:30 +00:00
969af57d65
Add a new ANY_EXTEND node, which operates like an extension but has undefined
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top bits.
llvm-svn: 23200
2005-09-02 00:14:40 +00:00
97ac77fd91
This should permit NOT and's, not even dead ones.
...
llvm-svn: 23199
2005-09-02 00:13:56 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
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the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
907123b1ab
Another case that shouldn't have sign extends: functions returning short
...
are known to return properly sign extended values, no need for an explicit
extension.
llvm-svn: 23197
2005-09-01 23:43:58 +00:00
d78d975437
Fix some code in the current node combining code, spotted when it was moved
...
over to DAGCombiner.cpp
1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
MaskedValueIsZero
llvm-svn: 23196
2005-09-01 23:25:49 +00:00
2504fe2613
Implement first round of feedback from chris (there's still a couple things
...
left to do).
llvm-svn: 23195
2005-09-01 23:24:04 +00:00
68d15fdfea
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
...
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
llvm-svn: 23194
2005-09-01 23:08:50 +00:00
e40a3ccd60
Local labels on darwin apparently start with just 'L', not .L like other
...
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
llvm-svn: 23193
2005-09-01 21:48:35 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
...
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
3fee6a51a9
This new class provides support for platform specific "features". The intent
...
is to manage processor specific attributes from the command line. See examples
of use in llc/lli and PowerPCTargetSubtarget.
llvm-svn: 23191
2005-09-01 21:36:18 +00:00
a305d28cf6
Implement dynamic allocas correctly. In particular, because we were copying
...
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
llvm-svn: 23190
2005-09-01 21:31:30 +00:00
293b3a68e0
Fix a bug where we were useing HA to get the high part, which seems like it
...
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
llvm-svn: 23189
2005-09-01 19:38:28 +00:00
34182aff7f
Do not select the operands being passed into SelectCC. IT does this itself
...
and selecting early prevents folding immediates into the cmpw* instructions
llvm-svn: 23188
2005-09-01 19:20:44 +00:00
975f5c9f46
It is NDEBUG not _NDEBUG
...
llvm-svn: 23186
2005-09-01 18:44:10 +00:00
e8f78d1aab
Add the rest of the currently implemented visit routines to the switch
...
statement in visit().
llvm-svn: 23185
2005-09-01 00:33:32 +00:00
21158fc485
First pass at the DAG Combiner. It isn't used anywhere yet, but it should
...
be mostly functional. It currently has all folds from SelectionDAG.cpp
that do not involve a condition code.
llvm-svn: 23184
2005-09-01 00:19:25 +00:00
13990fc286
Add regression test for efficient codegen of i32 x i32 -> hi32(i64) as
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mulhs.
llvm-svn: 23183
2005-09-01 00:04:03 +00:00
b3d2e7905f
remove an inappropriate comment
...
llvm-svn: 23182
2005-08-31 22:49:51 +00:00
d4d10fff99
If a function has live ins/outs, print them
...
llvm-svn: 23181
2005-08-31 22:34:59 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
6bad1fb19e
Remove dead code
...
llvm-svn: 23179
2005-08-31 20:25:15 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
3a04a4b767
Remove code that is now dead from the pattern isel.
...
llvm-svn: 23177
2005-08-31 19:11:36 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
8a1a5f2818
Allow targets to custom expand shifts that are too large for their registers
...
llvm-svn: 23173
2005-08-31 19:01:53 +00:00
0e6b11da03
Add a testcase for nate's patch
...
llvm-svn: 23172
2005-08-31 18:19:50 +00:00
2bd2af8ecd
add assert zext/sext to the dag isel
...
llvm-svn: 23171
2005-08-31 18:08:46 +00:00
46ff6aa993
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
...
llvm-svn: 23170
2005-08-31 17:48:04 +00:00
d8c84e3c7e
Fix VC++ precedence warnings
...
llvm-svn: 23169
2005-08-31 02:47:06 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
f4d594370b
Fix 'ret long' to return the high and lo parts in the right registers. This
...
fixes crafty and probably others.
llvm-svn: 23167
2005-08-31 01:34:29 +00:00
539e7c892c
Sigh, not my day. Fix typo.
...
llvm-svn: 23166
2005-08-31 00:43:49 +00:00
d513d8a662
Fix a mistake in my previous patch pointed out by sabre; the AssertZext
...
case in MaskedValueIsZero was wrong.
llvm-svn: 23165
2005-08-31 00:43:08 +00:00
e07bc28cca
Remove some unnecessary casts, and add the AssertZext case to
...
MaskedValueIsZero.
llvm-svn: 23164
2005-08-31 00:27:53 +00:00
ad688ddb20
Add support for count trailing zeroes, and population count. These are
...
needed for folding constants in the upcoming dag combiner.
llvm-svn: 23163
2005-08-31 00:25:01 +00:00
69e9a9a94c
now that physregs can exist in the same dag with multiple types, remove some
...
ugly hacks
llvm-svn: 23162
2005-08-30 22:59:48 +00:00
5764da422a
Allow physregs to occur in the dag with multiple types. Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :(
...
This fixes compilation of mesa
llvm-svn: 23161
2005-08-30 22:38:38 +00:00
1864662d5c
Allow physregs to occur in the dag with multiple types. Though I don't like
...
this, it is a requirement on PPC, which can have an f32 value in r3 at one
point in a function and a f64 value in r3 at another point. :(
llvm-svn: 23160
2005-08-30 22:38:05 +00:00
8f8d539746
Fix type mismatches when passing f32 values to calls
...
llvm-svn: 23159
2005-08-30 21:28:19 +00:00
4d602bed10
When checking the fixed intervals, don't forget to check for register aliases.
...
This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
llvm-svn: 23158
2005-08-30 21:03:36 +00:00
38b3704d28
new testcase corresponding to PR621
...
llvm-svn: 23157
2005-08-30 21:02:51 +00:00
2188b4363f
The dag isel misses both of these, the pattern isel just misses the second
...
one. TODO :)
llvm-svn: 23156
2005-08-30 18:44:09 +00:00
9f23ae226f
Fix some indentation (first hunks).
...
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
llvm-svn: 23155
2005-08-30 18:37:48 +00:00
6a41fd75cd
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
...
fixes fourinarow
llvm-svn: 23153
2005-08-30 17:42:59 +00:00
bdf3d3defb
codegen ADD_PARTS correctly: put the results in the right registers! This
...
fixes fhourstones
llvm-svn: 23152
2005-08-30 17:40:13 +00:00
61d21b1f3c
Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result
...
to SHIFT_PARTS nodes
llvm-svn: 23151
2005-08-30 17:21:17 +00:00
45706e9fb8
add operands in the right order, fixing McCat/18-imp with the dag isel
...
llvm-svn: 23150
2005-08-30 17:13:58 +00:00
9a4ad487f0
Fix a miscompile of PtrDist/bc. Sign extending bools is not the right thing,
...
at least tends to expose problems elsewhere.
llvm-svn: 23149
2005-08-30 16:56:19 +00:00
Chris Lattner