9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
811dd8d009
remove always-null IntrinsicLowering argument.
...
llvm-svn: 26971
2006-03-23 05:28:02 +00:00
0b2de9f2d4
remove the intrinsiclowering hook
...
llvm-svn: 26970
2006-03-23 05:22:51 +00:00
7055878170
Add v4i32 <-> v4f32 bitconvert patterns.
...
llvm-svn: 26969
2006-03-23 02:36:37 +00:00
eb0ce0c547
Allow result node to be a simple leaf node. This enable bitconvert patterns
...
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
llvm-svn: 26968
2006-03-23 02:35:32 +00:00
b9b0550dc6
Add 128-bit integer vector load and add (for testing).
...
llvm-svn: 26967
2006-03-23 01:57:24 +00:00
fb6e02931c
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
021bb7c956
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
...
64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
8e4c9ff3dc
Replace vector splat test case.
...
llvm-svn: 26963
2006-03-22 21:39:25 +00:00
fce9a3396b
Add a v2f64 splat (using movlhps) test case.
...
llvm-svn: 26962
2006-03-22 20:29:11 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
85633ae8f6
Fix comments
...
llvm-svn: 26960
2006-03-22 20:09:04 +00:00
ed794cd27b
SHUFP* are two address code.
...
llvm-svn: 26959
2006-03-22 20:08:18 +00:00
8070c02c2b
add a new node
...
llvm-svn: 26958
2006-03-22 19:56:46 +00:00
bc04722860
Some clean up.
...
llvm-svn: 26957
2006-03-22 19:22:18 +00:00
d4e1557941
- Supposely movlhps is faster / better than unpcklpd.
...
- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
35079019fc
test that vspltw is generated for test cases
...
llvm-svn: 26955
2006-03-22 19:12:46 +00:00
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
...
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
7d80b4f366
silence a bogus gcc warning
...
llvm-svn: 26953
2006-03-22 17:27:24 +00:00
6f682b79af
These changes are necessary to support the new llvm-config tool. llvm-config
...
is a handy tool for users of LLVM who want to be able to quickly get
information about LLVM's configuration. It is intended to be used in the
command line of other tools. Documentation will be forthcoming in a
subsequent patch.
llvm-svn: 26952
2006-03-22 15:59:55 +00:00
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
...
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
e24cf9dfa1
add a note
...
llvm-svn: 26950
2006-03-22 07:33:46 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
...
llvm-svn: 26949
2006-03-22 07:10:28 +00:00
2d52c1b8b9
Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries.
...
Now you can build a tool with just the JIT or just the interpreter.
llvm-svn: 26946
2006-03-22 06:07:50 +00:00
d3a3365904
wrap lines to 80 columns.
...
Add static JITCtor/InterpCtor fields
llvm-svn: 26945
2006-03-22 06:06:37 +00:00
eccf46950c
This has been implemented. Tweak it into another note
...
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
77373d1bea
Add support for "ri" addressing modes where the immediate is a 14-bit field
...
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
f5e36c8bc0
fix a warning
...
llvm-svn: 26941
2006-03-22 04:18:34 +00:00
d097e67544
Some splat and shuffle support.
...
llvm-svn: 26940
2006-03-22 02:53:00 +00:00
b1d3c64d1f
Add a couple more pseudo instructions.
...
llvm-svn: 26939
2006-03-22 02:52:03 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
baea59c61c
Didn't mean to check this in. No MMX support yet.
...
llvm-svn: 26933
2006-03-21 23:04:23 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
...
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
00f4683bf6
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
c0af9c6478
Don't forget to promote xform function to an explicit node for def : Pat<>
...
patterns.
llvm-svn: 26929
2006-03-21 20:44:17 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
0d776c5377
add some nodes for extractelement
...
llvm-svn: 26927
2006-03-21 20:43:08 +00:00
3a2ae6ad3c
Don't emit pseudo instructions!
...
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
013127981a
Update readme
...
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
a7afeff875
Add an integer splat test
...
llvm-svn: 26923
2006-03-21 18:27:27 +00:00
139eac5b71
Print absolute memory references like this:
...
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
2d819f5fa4
Combine 2 entries
...
llvm-svn: 26921
2006-03-21 07:18:26 +00:00
aeebc96099
Add a note about x86 register coallescing
...
llvm-svn: 26920
2006-03-21 07:12:57 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
02ad00ad93
minor code simplification
...
llvm-svn: 26918
2006-03-21 06:42:58 +00:00
bda7310ef7
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
...
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
1e2433f703
Cause the various warnings list to be generated via a <ul> list with
...
text enclosed in <tt>. This ensures that (a) the text is in a fixed width
font (to indicated generated text) and (b) the text wraps without causing
the page width to be extended. The main result of this is that the report
will wrap to conform to the window size in which it is displayed instead of
having a very wide length if a warning message is long.
llvm-svn: 26916
2006-03-21 01:21:39 +00:00
0f546dd9ca
Document ENABLE_ASSERTIONS=1
...
llvm-svn: 26915
2006-03-21 01:10:57 +00:00
98c79c34ef
Enable assertions to be enabled in release builds by building with
...
make ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1
llvm-svn: 26914
2006-03-21 01:06:41 +00:00
d2132f87d7
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
f194834161
minor note
...
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
...
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
fb872b41c0
Junk unused vector register classes.
...
llvm-svn: 26910
2006-03-21 00:30:59 +00:00
af7de1fba8
The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
...
one, i.e. don't select it.
llvm-svn: 26909
2006-03-20 22:53:06 +00:00
c8b16d00b9
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
6d74b09da7
remove dead variable
...
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
38f0894066
new testcase
...
llvm-svn: 26906
2006-03-20 22:37:05 +00:00
00f35f4e24
Move some common data structures between dom and pdom into the base class
...
llvm-svn: 26905
2006-03-20 19:32:48 +00:00
a1bc294f0c
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
9197775968
Option -enable-x86-lsr has been removed
...
llvm-svn: 26903
2006-03-20 18:26:11 +00:00
eda030da04
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
5ece6fa3e0
It should be ok for a xform output type to be different from input type.
...
llvm-svn: 26899
2006-03-20 08:09:17 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
80b6bd2746
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
e6448448c2
Move a few things around.
...
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
a84bdebfd2
Copy matching pattern's output type info to instruction result pattern.
...
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.
llvm-svn: 26892
2006-03-20 06:04:09 +00:00
e4e1ac37ba
add vector_shuffle
...
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
c1b31d8a83
Add a new SDTCisIntVectorOfSameSize type constraint
...
llvm-svn: 26890
2006-03-20 05:39:48 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
15ab90ae46
Add some helper methods
...
llvm-svn: 26882
2006-03-20 00:55:52 +00:00
bf21b32e98
Add another helper
...
llvm-svn: 26881
2006-03-20 00:20:30 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
979d260805
add a node
...
llvm-svn: 26879
2006-03-19 23:42:51 +00:00
07e9d9dd47
Add a helper method
...
llvm-svn: 26878
2006-03-19 23:41:32 +00:00
d16f6fdd49
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
d2ff59bfed
The library dependency file in flat format. This file is generated by the
...
makefile using the utils/GenLibDeps.pl script with the -flat option. It
records the dependencies between libraries in such a way that the
llvm-config script can easily read it (in makefile dependency format).
llvm-svn: 26876
2006-03-19 22:12:30 +00:00
80354c069a
First cut at the Makefile for llvm-config. This initial version just provides
...
the rule for building the LibDeps.txt file using GenLibDeps.pl. This needs
to be done from time to time manually in order to keep LibDeps.txt up to
date.
llvm-svn: 26875
2006-03-19 22:10:53 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
89f33a14b8
Add a -flat option for generating the library dependencies in a flat
...
format with one library per line, similar to a makefile dependency list.
llvm-svn: 26873
2006-03-19 22:08:01 +00:00
d783c76c18
Teach cee to propagate through switch statements. This implements
...
Transforms/CorrelatedExprs/switch.ll
Patch contributed by Eric Kidd!
llvm-svn: 26872
2006-03-19 19:37:24 +00:00
2a028e2f95
new testcase, contributed by Eric Kidd.
...
llvm-svn: 26871
2006-03-19 19:36:32 +00:00
f7c2e3628b
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
...
llvm-svn: 26869
2006-03-19 07:57:34 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0a03f789c2
Remind us of exit value substitution
...
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
5111c81a3c
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
66a9c0dea7
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
131cfed1c3
add a new testcase. This insertelement should be a noop on SSE.
...
llvm-svn: 26859
2006-03-19 05:46:51 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
d933ef93c4
improve comments, add a new MVT::getVectorBaseType method.
...
llvm-svn: 26855
2006-03-19 05:26:45 +00:00
1d09681edb
add another testcase, explicitly check stuff works with G5 and G3 codegen on
...
PPC.
llvm-svn: 26854
2006-03-19 04:45:11 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
891af0b15e
add two new insert_element tests
...
llvm-svn: 26850
2006-03-19 01:27:04 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
122b3accb6
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow
...
*BUILD_VECTOR to take variable inputs.
llvm-svn: 26846
2006-03-19 00:52:25 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
a982c7ee87
Add three new testcases
...
llvm-svn: 26844
2006-03-19 00:20:03 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
544dab3a35
update testcases for x86 fastcc changes.
...
llvm-svn: 26842
2006-03-18 23:48:54 +00:00
c28282bd87
- Fixed a bogus if condition.
...
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.
llvm-svn: 26841
2006-03-18 08:03:12 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
a956760359
Update comments.
...
llvm-svn: 26839
2006-03-18 01:43:28 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
f09f0ebd48
Sort StrideOrder so we can process the smallest strides first. This allows
...
for more IV reuses.
llvm-svn: 26837
2006-03-18 00:44:49 +00:00
f878f6aa54
Fix miscodegen of V_SET0 in PPC.
...
llvm-svn: 26836
2006-03-18 00:40:36 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
41767dd142
Add a missing testcase
...
llvm-svn: 26834
2006-03-17 22:39:45 +00:00
b09a56f3a4
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
da2b6ee1d6
new testcase
...
llvm-svn: 26832
2006-03-17 20:04:40 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
783ea16fe4
add a couple of enum values
...
llvm-svn: 26829
2006-03-17 19:53:41 +00:00
4520698820
Allow users of iv / stride to be rewritten with expression that is a multiply
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of a smaller stride even if they have a common loop invariant expression part.
llvm-svn: 26828
2006-03-17 19:52:23 +00:00
e28ad7eaf1
Add a lsr common loop invariant hoisting test case
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llvm-svn: 26827
2006-03-17 19:45:54 +00:00
8aa2b66653
new testcase that broke the new f.e.
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llvm-svn: 26826
2006-03-17 18:01:17 +00:00
d1453ef454
Use the <tt> tag instead of <pre> tag to get code/file/warning lists to
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wrap but also still be in a fixed-width font.
llvm-svn: 26825
2006-03-17 17:43:01 +00:00
388fc4d9fb
Disable x86 fastcc from passing args in registers
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llvm-svn: 26824
2006-03-17 17:27:47 +00:00
dca24a1f02
Fix a typo.
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llvm-svn: 26823
2006-03-17 08:04:25 +00:00
779c10818c
Fix use of LEVEL.
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llvm-svn: 26822
2006-03-17 07:39:44 +00:00
ee4b4f55ee
Two fixes:
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1. Allow building of Intrinsics.gen to work for srcdir != objdir
2. Add a rule for installation of Intrinsics.gen.
llvm-svn: 26819
2006-03-17 06:27:06 +00:00
43798850f9
Parameterize the number of integer arguments to pass in registers
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llvm-svn: 26818
2006-03-17 05:10:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
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llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
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ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
Chris Lattner