eda030da04
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
80b6bd2746
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
e6448448c2
Move a few things around.
...
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
e4e1ac37ba
add vector_shuffle
...
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
d16f6fdd49
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
d783c76c18
Teach cee to propagate through switch statements. This implements
...
Transforms/CorrelatedExprs/switch.ll
Patch contributed by Eric Kidd!
llvm-svn: 26872
2006-03-19 19:37:24 +00:00
f7c2e3628b
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0a03f789c2
Remind us of exit value substitution
...
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
5111c81a3c
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
66a9c0dea7
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
c28282bd87
- Fixed a bogus if condition.
...
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.
llvm-svn: 26841
2006-03-18 08:03:12 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
f09f0ebd48
Sort StrideOrder so we can process the smallest strides first. This allows
...
for more IV reuses.
llvm-svn: 26837
2006-03-18 00:44:49 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
b09a56f3a4
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
4520698820
Allow users of iv / stride to be rewritten with expression that is a multiply
...
of a smaller stride even if they have a common loop invariant expression part.
llvm-svn: 26828
2006-03-17 19:52:23 +00:00
388fc4d9fb
Disable x86 fastcc from passing args in registers
...
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
779c10818c
Fix use of LEVEL.
...
llvm-svn: 26822
2006-03-17 07:39:44 +00:00
ee4b4f55ee
Two fixes:
...
1. Allow building of Intrinsics.gen to work for srcdir != objdir
2. Add a rule for installation of Intrinsics.gen.
llvm-svn: 26819
2006-03-17 06:27:06 +00:00
43798850f9
Parameterize the number of integer arguments to pass in registers
...
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
27750f3287
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
8bf1c59e7f
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
c11fcceec5
A new entry.
...
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
fb0e36fa56
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
1e6dfa4c1f
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
325bb46315
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
91400bd413
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
f75555feb9
Bug fix: condition inverted.
...
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
3df447d354
For each loop, keep track of all the IV expressions inserted indexed by
...
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV expression. Rather, reuse the
previous IV and rewrite the uses as uses of IV expression multiplied by
the factor.
e.g.
x = 0 ...; x ++
y = 0 ...; y += 4
then use of y can be rewritten as use of 4*x for x86.
llvm-svn: 26803
2006-03-16 21:53:05 +00:00
20931a798e
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
0b27047a6c
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
ad74844bfa
set TransformToType correctly for vector types.
...
llvm-svn: 26797
2006-03-16 19:50:01 +00:00
32e73f9881
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
1678a6c477
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
4b41e40621
add support for the bitconvert node
...
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
6d6084fd04
Teach the strip pass to strip type names in addition to value names. This
...
is fallout from the type/value split in the symtab long long ago :)
llvm-svn: 26785
2006-03-15 19:22:41 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b3dae7cfa9
no heap is happening here
...
llvm-svn: 26781
2006-03-15 19:03:16 +00:00
c0b65305f1
remove qsort for now
...
llvm-svn: 26779
2006-03-15 18:32:18 +00:00
fb4df2055f
allow field sensitivity to be a tunable parameter
...
llvm-svn: 26777
2006-03-15 05:43:41 +00:00
2e1fde7c5c
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
3196422df0
Handle one offset with growth case seen in povray. Namely, if we have an offset,
...
and the offset lands at a field boundary in the old type, construct a new type,
copying the fields masked by the offset from the old type, and unify with that.
llvm-svn: 26775
2006-03-15 04:04:21 +00:00
c254e5b180
improve mem intrinsics and add a few things povray uses
...
llvm-svn: 26774
2006-03-15 03:43:59 +00:00
6995470323
Bugfix, unbreaking CodeGen/PowerPC/cttz.ll
...
llvm-svn: 26764
2006-03-14 19:49:57 +00:00
6d4a221d80
Fix an et-forest memory leak. Patch by Daniel Berlin.
...
llvm-svn: 26763
2006-03-14 19:41:45 +00:00
5271a1f9b5
add a note
...
llvm-svn: 26762
2006-03-14 19:31:24 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
ab1ed2aa96
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
c5f866bb4a
Implement a FIXME, recusively reassociating
...
A*A*B + A*A*C --> A*(A*B+A*C) --> A*(A*(B+C))
This implements Reassociate/mul-factor3.ll
llvm-svn: 26757
2006-03-14 16:04:29 +00:00
2fc319d444
extract some code into a method, no functionality change
...
llvm-svn: 26755
2006-03-14 07:11:11 +00:00
30402be175
transformation implemented
...
llvm-svn: 26754
2006-03-14 06:57:34 +00:00
d6bde46d85
Promote shifts by a constant to multiplies so that we can reassociate
...
(x<<1)+(y<<1) -> (X+Y)<<1. This implements
Transforms/Reassociate/shift-factor.ll
llvm-svn: 26753
2006-03-14 06:55:18 +00:00
c67a060a51
Convert llvm.cs.uiuc.edu -> llvm.org
...
llvm-svn: 26748
2006-03-14 05:54:52 +00:00
cf0bdffe6d
1. Handle removal of all arguments for a morphed intrinsic.
...
2. Remove the declaration of llvm.dbg.declare.
llvm-svn: 26745
2006-03-14 02:00:35 +00:00
0f9d6534f5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
60f495100a
Update
...
llvm-svn: 26741
2006-03-13 23:19:10 +00:00
af598d2461
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
c567c4efbb
Added target lowering hooks which LSR consults to make more intelligent
...
transformation decisions.
llvm-svn: 26738
2006-03-13 23:14:23 +00:00
2b8eb375d7
Handle builtins that directly correspond to GCC builtins.
...
llvm-svn: 26737
2006-03-13 23:09:05 +00:00
02e2c18c9c
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
611f965820
Bring makefile back into compliance with standard by using
...
$(Echo) instead of @echo
llvm-svn: 26730
2006-03-13 17:57:31 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
fe4c7fb7ae
remove two implemented items
...
llvm-svn: 26728
2006-03-13 06:52:22 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
3d761b6211
I can't convince myself that this is safe, remove the recursive call.
...
llvm-svn: 26725
2006-03-13 06:42:16 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
d03132a409
blr is a branch too
...
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
4e56b686f1
add an example
...
llvm-svn: 26709
2006-03-11 20:20:40 +00:00
003f633036
add a note
...
llvm-svn: 26708
2006-03-11 20:17:08 +00:00
d5811b965d
Fix PR681 by using the standard Lengauer and Tarjan algorithm for dominator
...
set construction, rather than intersecting various std::sets. This reduces
the memory usage for the testcase in PR681 from 496 to 26MB of ram on my
darwin system, and reduces the runtime from 32.8 to 0.8 seconds on a
2.5GHz G5. This also enables future code sharing between Dom and PostDom
now that they share near-identical implementations.
llvm-svn: 26707
2006-03-11 02:20:46 +00:00
2c5e530430
Doh!
...
llvm-svn: 26705
2006-03-11 00:13:10 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
8a18a823a0
remove some dead code
...
llvm-svn: 26703
2006-03-10 23:14:22 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
7d587f37ec
Remove UnixLocalInferiorProcess: debugging via the JIT isn't a good idea.
...
Perhaps llvm-db will turn into a read debugger someday.
llvm-svn: 26700
2006-03-10 22:39:48 +00:00
c2447e8b59
teach the JIT to encode vector registers
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llvm-svn: 26697
2006-03-10 20:19:50 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
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llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
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llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
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llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
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llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
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llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
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llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
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llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
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llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
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llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
60f6833376
use autogenerated side-effect information
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llvm-svn: 26673
2006-03-09 22:38:10 +00:00
bb40a9fa58
Use autogenerated mod/ref info for intrinsics.
...
llvm-svn: 26670
2006-03-09 22:31:29 +00:00
591693f3bf
Use the autogenerated intrinsic verifier
...
llvm-svn: 26667
2006-03-09 22:06:04 +00:00
Chris Lattner