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13474 Commits

Author SHA1 Message Date
Chris Lattner ba38035e21 Make sure to pass enough values to phi nodes when we are dealing with 
decimated vectors.  This fixes UnitTests/Vector/sumarray-dbl.c

llvm-svn: 27280
 2006-03-31 02:12:18 +00:00
Chris Lattner 5fe1f54c17 Significantly improve handling of vectors that are live across basic blocks, 
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.

llvm-svn: 27278
 2006-03-31 02:06:56 +00:00
Chris Lattner 051f7861b8 Was returning the wrong type. 
llvm-svn: 27277
 2006-03-31 01:50:09 +00:00
Chris Lattner bca5fbe914 Mark INSERT_VECTOR_ELT as expand 
llvm-svn: 27276
 2006-03-31 01:48:55 +00:00
Evan Cheng 1b0d294de0 Expand all INSERT_VECTOR_ELT (obviously bad) for now. 
llvm-svn: 27275
 2006-03-31 01:30:39 +00:00
Evan Cheng 168e45b0b3 Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp; 
llvm-svn: 27274
 2006-03-31 01:27:51 +00:00
Chris Lattner f144dac7b7 Modify the TargetLowering::getPackedTypeBreakdown method to also return the 
unpromoted element type.

llvm-svn: 27273
 2006-03-31 00:46:36 +00:00
Evan Cheng d9d0bbb5ac Typo 
llvm-svn: 27272
 2006-03-31 00:33:57 +00:00
Evan Cheng 99d7205fba Ok for vector_shuffle mask to contain undef elements. 
llvm-svn: 27271
 2006-03-31 00:30:29 +00:00
Chris Lattner 549fb167eb Implement TargetLowering::getPackedTypeBreakdown 
llvm-svn: 27270
 2006-03-31 00:28:56 +00:00
Chris Lattner c4e3eadf21 Add the rest of the vmul instructions and the vmulsum* instructions. 
llvm-svn: 27268
 2006-03-30 23:39:06 +00:00
Chris Lattner a23158f1ca Use a new tblgen feature to significantly shrinkify instruction definitions that 
directly correspond to intrinsics.

llvm-svn: 27266
 2006-03-30 23:21:27 +00:00
Chris Lattner 551d3a11d3 Add a bunch of new instructions for intrinsics. 
llvm-svn: 27265
 2006-03-30 23:07:36 +00:00
Chris Lattner 612fa8e6f3 Fix Transforms/InstCombine/2006-03-30-ExtractElement.ll 
llvm-svn: 27261
 2006-03-30 22:02:40 +00:00
Evan Cheng 7e2ff11a42 Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
 2006-03-30 19:54:57 +00:00
Evan Cheng dd487d865b More logical ops patterns 
llvm-svn: 27257
 2006-03-30 07:33:32 +00:00
Evan Cheng c58ef7deeb Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng 593310016d Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng c5cf9bba05 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng b7fedffc78 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
 2006-03-29 23:07:14 +00:00
Evan Cheng acc336475e Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng 3cf95747c7 Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00
Evan Cheng 500ec16578 - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
 2006-03-29 03:04:49 +00:00
Evan Cheng 3a1c4e75de Another entry about shuffles. 
llvm-svn: 27245
 2006-03-29 03:03:46 +00:00
Evan Cheng da59b0d2a8 - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.

llvm-svn: 27244
 2006-03-29 01:30:51 +00:00
Chris Lattner 7d6f4f14b4 add a note 
llvm-svn: 27243
 2006-03-29 00:24:13 +00:00
Chris Lattner 67271869a8 Bug fixes: handle constantexpr insert/extract element operations 
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll

llvm-svn: 27241
 2006-03-29 00:11:43 +00:00
Evan Cheng 38b34296d0 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
 2006-03-28 23:51:43 +00:00
Evan Cheng 8160fd3d42 Fixing buggy code. 
llvm-svn: 27239
 2006-03-28 23:41:33 +00:00
Chris Lattner 20e619fba3 When building a VVECTOR_SHUFFLE node from extract_element operations, make 
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from
matching.  For a particular splat, we go from generating this:

	li r10, lo16(LCPI1_0)
	lis r11, ha16(LCPI1_0)
	lvx v3, r11, r10
	vperm v3, v2, v2, v3

to generating:

	vspltw v3, v2, 3

llvm-svn: 27236
 2006-03-28 22:19:47 +00:00
Chris Lattner a46dfe80c8 Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y') 
llvm-svn: 27235
 2006-03-28 22:11:53 +00:00
Chris Lattner c9992548fc Turn a series of extract_element's feeding a build_vector into a 
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
        movl 8(%esp), %eax
        movaps (%eax), %xmm0
        movl 12(%esp), %eax
        unpcklps (%eax), %xmm0
        movl 4(%esp), %eax
        movaps %xmm0, (%eax)
        ret

instead of this:

_test:
        subl $76, %esp
        movl 88(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, (%esp)
        movaps %xmm0, 32(%esp)
        movss 4(%esp), %xmm0
        movss 32(%esp), %xmm1
        unpcklps %xmm0, %xmm1
        movl 84(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, 16(%esp)
        movaps %xmm0, 48(%esp)
        movss 20(%esp), %xmm0
        movss 48(%esp), %xmm2
        unpcklps %xmm0, %xmm2
        unpcklps %xmm1, %xmm2
        movl 80(%esp), %eax
        movaps %xmm2, (%eax)
        addl $76, %esp
        ret

GCC produces this (with -fomit-frame-pointer):

_test:
        subl    $12, %esp
        movl    20(%esp), %eax
        movaps  (%eax), %xmm0
        movl    24(%esp), %eax
        unpcklps        (%eax), %xmm0
        movl    16(%esp), %eax
        movaps  %xmm0, (%eax)
        addl    $12, %esp
        ret

llvm-svn: 27233
 2006-03-28 20:28:38 +00:00
Chris Lattner f6f94d3bce Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes. 
llvm-svn: 27232
 2006-03-28 20:24:43 +00:00
Chris Lattner 8d57da2ffc new node 
llvm-svn: 27231
 2006-03-28 19:54:42 +00:00
Chris Lattner b7163598f9 Don't crash on X^X if X is a vector. Instead, produce a vector of zeros. 
llvm-svn: 27229
 2006-03-28 19:11:05 +00:00
Chris Lattner ffec47ebff Add an assertion 
llvm-svn: 27228
 2006-03-28 19:04:49 +00:00
Chris Lattner 66e1410858 add a note 
llvm-svn: 27227
 2006-03-28 18:56:23 +00:00
Jim Laskey dea0348853 Refactor address attributes. Add base register to frame info. 
llvm-svn: 27226
 2006-03-28 14:58:32 +00:00
Jim Laskey d1aa1638c6 Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey 67a636c587 More bulletproofing of llvm.dbg.declare. 
llvm-svn: 27224
 2006-03-28 13:45:20 +00:00
Jim Laskey 457e54efc1 Added missing paren on behalf of Ramana Radhakrishnan. 
llvm-svn: 27223
 2006-03-28 10:17:11 +00:00
Evan Cheng 21e5476deb Missed X86::isUNPCKHMask 
llvm-svn: 27222
 2006-03-28 08:27:15 +00:00
Evan Cheng be2d9a0e99 movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng dc57ae0711 Update 
llvm-svn: 27220
 2006-03-28 06:55:45 +00:00
Evan Cheng 4e7374ff8a Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00
Evan Cheng 1a194a5264 * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.

llvm-svn: 27218
 2006-03-28 06:50:32 +00:00
Nate Begeman af8c373e77 Fix a couple typos 
llvm-svn: 27216
 2006-03-28 04:18:18 +00:00
Nate Begeman 1b3928765d Add a few more altivec intrinsics 
llvm-svn: 27215
 2006-03-28 04:15:58 +00:00
Evan Cheng 08b473c619 Added a couple of entries about movhps and movlhps. 
llvm-svn: 27212
 2006-03-28 02:49:12 +00:00
Evan Cheng 3765fadef6 All unpack cases are now being handled. 
llvm-svn: 27211
 2006-03-28 02:44:05 +00:00