1ff71872c2
Honor user-defined section specification of a global, ignores whether its initializer is null.
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llvm-svn: 42182
2007-09-21 00:41:19 +00:00
d29f938335
Do not override user specified section.
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llvm-svn: 42179
2007-09-20 23:07:37 +00:00
9da02f5ee2
Remove isReg, isImm, and isMBB, and change all their users to use
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isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
5196f617a1
Fix comments.
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llvm-svn: 41947
2007-09-14 01:57:02 +00:00
66c22e8fd6
Enable indirect encoding for the personality function
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llvm-svn: 41873
2007-09-11 23:55:40 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
6777b72659
Add some notes about better flag handling.
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llvm-svn: 41808
2007-09-10 21:43:18 +00:00
9929bc403d
Add missing index versions of instructions to the map.
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llvm-svn: 41776
2007-09-07 22:01:02 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
b65ef38590
LVXL and STVXL are also a load and store resp.
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llvm-svn: 41733
2007-09-05 23:47:12 +00:00
b9bf812ba5
Add the 64-bit versions of the DS* Altivec instructions.
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llvm-svn: 41717
2007-09-05 04:05:20 +00:00
4dbd9f254a
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
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llvm-svn: 41711
2007-09-04 20:20:29 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
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Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
9a25d98c86
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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llvm-svn: 41597
2007-08-30 05:52:20 +00:00
10e18dea2a
Use i64 on a PPC64 machine
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llvm-svn: 41590
2007-08-30 00:59:19 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
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changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
a124f69c52
Disable EH generation until PPC works 100%.
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llvm-svn: 41360
2007-08-24 16:00:15 +00:00
92c6a65d4e
new example
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llvm-svn: 41318
2007-08-23 15:16:03 +00:00
f5124b36e4
Fix arguments for some Altivec instructions. From SWB.
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llvm-svn: 40957
2007-08-09 00:49:19 +00:00
4e7ff3593c
Fix spelling of mtvscr and mfvscr.
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llvm-svn: 40908
2007-08-07 23:08:00 +00:00
c5283ecd6f
long double patch 2 of N. Handle it in TargetData.
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(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
llvm-svn: 40792
2007-08-03 20:20:50 +00:00
5f6a9da530
More explicit keywords.
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llvm-svn: 40757
2007-08-02 21:21:54 +00:00
58c3c30921
Some out operands were incorrectly specified as input operands.
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llvm-svn: 40697
2007-08-01 23:07:38 +00:00
581d2795dc
Vector fneg must be expanded into fsub -0.0, X.
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llvm-svn: 40586
2007-07-30 07:51:22 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
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still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
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AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
5805c46e8f
Fix debug info and globals filled with zeros.
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llvm-svn: 40483
2007-07-25 03:48:45 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
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llvm-svn: 40123
2007-07-20 21:56:13 +00:00
9081ab8127
Oops. These stores actually produce results.
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llvm-svn: 40074
2007-07-20 00:20:46 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
383a324735
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
09d73c0305
Assert when TLS is not implemented.
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llvm-svn: 39737
2007-07-11 17:19:51 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
ea4a82bcfb
PPC conditional branch predicate does not change after isel.
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llvm-svn: 37893
2007-07-05 07:09:50 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
58d1eacd80
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
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llvm-svn: 37790
2007-06-29 01:25:06 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
7936d91f70
describe an argument, hide it.
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llvm-svn: 37650
2007-06-19 05:46:06 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
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Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
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llvm-svn: 37579
2007-06-14 22:58:02 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
cff3e122b0
Implementation of compilation callback in PPC ELF32
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llvm-svn: 37340
2007-05-29 16:33:18 +00:00
f9cbdc676c
name change requested by review of previous patch
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llvm-svn: 37289
2007-05-22 18:31:04 +00:00
Evan Cheng