54a2c32670
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
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expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
llvm-svn: 98168
2010-03-10 18:12:27 +00:00
54dfa01adc
Lower add (mul a, b), c into MACCU / MACCS nodes which translate
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directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
llvm-svn: 98150
2010-03-10 11:41:08 +00:00
e35eabdd69
Convert test to FileCheck.
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llvm-svn: 98148
2010-03-10 11:24:03 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
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llvm-svn: 81293
2009-09-09 00:09:15 +00:00
5fe5933909
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
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these operations if ladd/lsub are not available on the current
subtarget.
llvm-svn: 59305
2008-11-14 15:59:19 +00:00
Richard Osborne