Commit Graph

46304 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 36b5d8a698 Break the spill placement algorithm into three parts: prepare, addConstraints, and finish.
This will allow us to abort the algorithm early if it is determined to be futile.

llvm-svn: 129020
2011-04-06 19:13:57 +00:00
Johnny Chen 8bca174f48 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Rafael Espindola b4dd95b4f9 Add another case we are not optimizing.
llvm-svn: 129012
2011-04-06 17:35:32 +00:00
Rafael Espindola 7a3b244d45 The original issue has been fixed by not doing unnecessary sign extensions.
Change the test to force a sign extension and expose the problem again.

llvm-svn: 129011
2011-04-06 17:19:35 +00:00
Devang Patel 8aa6c326ac face+palm
Keep track of llvm.dbg.value intrinsics with non null values.

llvm-svn: 129010
2011-04-06 17:08:15 +00:00
Rafael Espindola 337a1b29e5 Do a topological sort of the types before writing them out.
This takes the linking of libxul on linux from 6m54.931s to 5m39.840s.

llvm-svn: 129009
2011-04-06 16:49:37 +00:00
Frits van Bommel 87e3367d32 Fix a few instances of "warning: extra ';' outside of a function [-pedantic]".
llvm-svn: 129002
2011-04-06 12:29:56 +00:00
Nick Lewycky d4b3d29c50 Add an empty key for DebugLoc so that you can store an empty DebugLoc in a
DenseMap.

llvm-svn: 128994
2011-04-06 06:49:59 +00:00
Nick Lewycky ddc72895d0 Support using DebugLoc's in a DenseMap.
llvm-svn: 128988
2011-04-06 05:36:52 +00:00
Jakob Stoklund Olesen f3b2dcc74d Oops. Scary.
llvm-svn: 128986
2011-04-06 04:07:14 +00:00
Jakob Stoklund Olesen bf91c4e85e Analyze blocks with uses separately from live-through blocks without uses.
About 90% of the relevant blocks are live-through without uses, and the only
information required about them is their number. This saves memory and enables
later optimizations that need to look at only the use-blocks.

llvm-svn: 128985
2011-04-06 03:57:00 +00:00
Johnny Chen 0ec0e98a6a Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
2011-04-06 01:18:32 +00:00
Jim Grosbach 23de2437bd RuntimeDyld should use the memory manager API.
Start teaching the runtime Dyld interface to use the memory manager API
for allocating space. Rather than mapping directly into the MachO object,
we extract the payload for each object and copy it into a dedicated buffer
allocated via the memory manager. For now, just do Segment64, so this works
on x86_64, but not yet on ARM.

llvm-svn: 128973
2011-04-06 01:11:05 +00:00
Owen Anderson 867846b1f0 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
llvm-svn: 128965
2011-04-05 23:55:28 +00:00
Chandler Carruth 086f7080d6 Make the virtual destructor out-of-line so we have a key function.
llvm-svn: 128964
2011-04-05 23:54:31 +00:00
Jakob Stoklund Olesen 858afbb6ac Sign error
llvm-svn: 128963
2011-04-05 23:43:16 +00:00
Jakob Stoklund Olesen 5c482cd38f Don't crash when a value is defined after the last split point.
llvm-svn: 128962
2011-04-05 23:43:14 +00:00
Jakob Stoklund Olesen 30b5473d82 Permit blocks to branch directly to a landing pad.
Treat the landing pad as a normal successor when that happens.

llvm-svn: 128961
2011-04-05 23:43:11 +00:00
Jim Grosbach f642c1b600 Remove extraneous 'return'.
llvm-svn: 128959
2011-04-05 23:39:08 +00:00
Johnny Chen f6e327c6a3 Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Bob Wilson d135c696c0 Clean up some code for clarity.
llvm-svn: 128953
2011-04-05 23:03:25 +00:00
Owen Anderson 61e7a935bd Revert r128946 while I figure out why it broke the buildbots.
llvm-svn: 128951
2011-04-05 23:03:06 +00:00
Johnny Chen c3656d29f6 A7.3 register encoding
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Devang Patel 9f738849ab Add support to encode function's template parameters.
llvm-svn: 128947
2011-04-05 22:52:06 +00:00
Owen Anderson 3501655ad9 Give RSBS and RSCS the pseudo treatment.
llvm-svn: 128946
2011-04-05 22:42:54 +00:00
Johnny Chen 9da60e016b ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
2011-04-05 22:18:07 +00:00
Chris Lattner 57ee5a5db7 remove postdom frontiers, because it is dead. Forward dom frontiers are
still used by RegionInfo :(

llvm-svn: 128943
2011-04-05 21:57:17 +00:00
Johnny Chen 25883487a1 ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
2011-04-05 21:49:44 +00:00
Owen Anderson 77aa266de8 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
Jakob Stoklund Olesen 6aa0fbf4c0 Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.
llvm-svn: 128935
2011-04-05 21:40:37 +00:00
Devang Patel d4e20eacf0 Refactor.
llvm-svn: 128929
2011-04-05 21:08:24 +00:00
Bob Wilson 6c20b88173 Add an assertion instead of crashing when the scavenger goes past the end
of a basic block.

llvm-svn: 128925
2011-04-05 20:44:15 +00:00
Nick Lewycky ee54fa29d5 Fix typos. Adjust some whitespace for style. No functionality change.
llvm-svn: 128924
2011-04-05 20:39:27 +00:00
Johnny Chen e9c644d4a0 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
2011-04-05 20:32:23 +00:00
Roman Divacky 92d313a021 Add support for detection of Intel SandyBridge.
llvm-svn: 128920
2011-04-05 20:25:36 +00:00
Jakob Stoklund Olesen 18fd84c79a When dead code elimination removes all but one use, try to fold the single def into the remaining use.
Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

llvm-svn: 128918
2011-04-05 20:20:26 +00:00
Devang Patel 651d06e036 Do not emit empty name.
llvm-svn: 128914
2011-04-05 20:14:13 +00:00
Johnny Chen 151582492d ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
Andrew Trick 12004013ef Added *hidden* flags -print-options and -print-all-options so
developers can see if their driver changed any cl::Option's. The
current implementation isn't perfect but handles most kinds of
options. This is nice to have when decomposing the stages of
compilation and moving between different drivers. It's also a good
sanity check when comparing results produced by different command line
invocations that are expected to produce the comparable results.

Note: This is not an attempt to prolong the life of cl::Option. On the
contrary, it's a placeholder for a feature that must exist when
cl::Option is replaced by a more appropriate framework. A new
framework needs: a central option registry, dynamic name lookup,
non-global containers of option values (e.g. per-module,
per-function), *and* the ability to print options values and their defaults at
any point during compilation.

llvm-svn: 128910
2011-04-05 18:54:36 +00:00
Shantonu Sen e59f8ca49e An MCDisassembler has the option to not implement
getEDInfo(), in which case this code would dereference
NULL. EDInst can already handle NULL info, so avoid
the dereference and pass NULL through.

Reviewed by Sean Callanan

llvm-svn: 128904
2011-04-05 18:40:45 +00:00
Jim Grosbach d9dce561b6 Make second source operand of LDRD pre/post explicit.
Finish what r128736 started.

llvm-svn: 128903
2011-04-05 18:40:13 +00:00
Johnny Chen 33d3a9fadc Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
2011-04-05 18:02:46 +00:00
Johnny Chen 268d63f307 Check for invalid register encodings for UMAAL and friends where:
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
2011-04-05 17:43:10 +00:00
Owen Anderson f7678b83d2 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
Jakob Stoklund Olesen 76ad3debab Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

llvm-svn: 128888
2011-04-05 16:53:50 +00:00
Rafael Espindola 7dd4d6e2e8 Print visibility info for external variables.
llvm-svn: 128887
2011-04-05 15:51:32 +00:00
Jakob Stoklund Olesen fe6e07fd8a Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots.
This allows us to always keep the smaller slot for an instruction which is what
we want when a register has early clobber defines.

Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed.

llvm-svn: 128886
2011-04-05 15:18:18 +00:00
Nadav Rotem a069c6ce05 InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away address
space info. We crash with an assert in this case. This change checks that the
address space of the bitcasted pointer is the same as the gep ptr.

llvm-svn: 128884
2011-04-05 14:29:52 +00:00
Jakob Stoklund Olesen d93b0e3ced Stop precomputing last split points, query the SplitAnalysis cache on demand.
llvm-svn: 128875
2011-04-05 04:20:29 +00:00
Jakob Stoklund Olesen 50b2db8a02 Cache the fairly expensive last split point computation and provide a fast
inlined path for the common case.

Most basic blocks don't contain a call that may throw, so the last split point
os simply the first terminator.

llvm-svn: 128874
2011-04-05 04:20:27 +00:00