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168 Commits

Author SHA1 Message Date
Chris Lattner 687dbf1a99 tcl seems to hate |& for some reason. 
llvm-svn: 41073
 2007-08-14 16:19:35 +00:00
Chris Lattner 0e92458068 switch this to use fastcc to avoid fpstack traffic on x86-32. Switch to 
using the count script instead of wc -l

llvm-svn: 41072
 2007-08-14 16:14:10 +00:00
Evan Cheng 5c6d53d2ff Update test case. A spill should now be deleted. 
llvm-svn: 41070
 2007-08-14 09:16:00 +00:00
Evan Cheng 5e221dbe8f Spiller reuse test case. 
llvm-svn: 41068
 2007-08-14 05:51:03 +00:00
Evan Cheng 2814fe847d Now capable of rematerializing coalesced live intervals. 
llvm-svn: 41061
 2007-08-13 23:54:16 +00:00
Dan Gohman ccb3611881 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049
 2007-08-13 20:03:06 +00:00
Chris Lattner 4e7f673f65 Fix PR1607 
llvm-svn: 41048
 2007-08-13 18:42:37 +00:00
Christopher Lamb 030a59d967 Fix test so it passes. 
llvm-svn: 41012
 2007-08-10 22:20:57 +00:00
Christopher Lamb b372abab14 Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
llvm-svn: 41010
 2007-08-10 21:48:46 +00:00
Christopher Lamb d36d30b53c Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
llvm-svn: 41007
 2007-08-10 21:18:25 +00:00
Dan Gohman a17799a3bd Fix EXTRACT_ELEMENT, EXTRACT_SUBVECTOR, and EXTRACT_VECTOR_ELT to 
use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.

llvm-svn: 40987
 2007-08-10 14:59:38 +00:00
Chris Lattner 39d751058a allow this to pass on ppc hosts. 
llvm-svn: 40846
 2007-08-05 18:48:18 +00:00
Dan Gohman 8932bff7fe Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756
 2007-08-02 21:17:01 +00:00
Dan Gohman fa3eeeedc0 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736
 2007-08-02 14:27:55 +00:00
Evan Cheng 824693c87a Fix test. 
llvm-svn: 40721
 2007-08-02 05:04:16 +00:00
Evan Cheng 41ccce7169 New test. Bogus implicit-def prevented a copy from being coalesced. 
llvm-svn: 40690
 2007-08-01 20:26:40 +00:00
Chris Lattner 9182684222 we're now handling this right :) 
llvm-svn: 40675
 2007-08-01 17:10:30 +00:00
Evan Cheng 09a141df31 Requires SSE2. 
llvm-svn: 40657
 2007-08-01 00:10:12 +00:00
Dan Gohman 54ec4bfa5f Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
 2007-07-31 20:11:57 +00:00
Evan Cheng 12c6be84ff Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
llvm-svn: 40628
 2007-07-31 08:04:03 +00:00
Dan Gohman 4788552deb Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Evan Cheng 931de40afa Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng dfa5d283fd Test case for PR1573. 
llvm-svn: 40539
 2007-07-26 17:45:57 +00:00
Evan Cheng e9ba8e0765 Fix test. 
llvm-svn: 40536
 2007-07-26 17:07:03 +00:00
Dan Gohman 8455bd3fae Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Dan Gohman f906c7286f Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Dan Gohman 45863cc202 Update these regression tests to accomodate X86InstrSSE.td now using movups/movaps 
for everything.

llvm-svn: 40101
 2007-07-20 16:31:26 +00:00
Evan Cheng f195429a0e New test. 
llvm-svn: 40077
 2007-07-20 00:27:56 +00:00
Evan Cheng a39fd10e32 New test. 
llvm-svn: 40073
 2007-07-19 23:53:50 +00:00
Evan Cheng 8ab393548f Try fixing it again. 
llvm-svn: 40072
 2007-07-19 23:53:29 +00:00
Reid Spencer 314e1cb7ee For PR1553: 
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.

llvm-svn: 40069
 2007-07-19 23:13:04 +00:00
Bill Wendling dd96b98bf6 Don't need the "&&" to glue lines together. 
llvm-svn: 40063
 2007-07-19 18:06:26 +00:00
Bill Wendling e8ea3303ce Testcase for PR1549 
llvm-svn: 40041
 2007-07-19 06:31:11 +00:00
Evan Cheng dcc3451f8a New test. 
llvm-svn: 40020
 2007-07-18 21:39:16 +00:00
Dan Gohman 776962a97a Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Dan Gohman a7b65c30a3 It's not necessary to do rounding for alloca operations when the requested 
alignment is equal to the stack alignment.

llvm-svn: 40004
 2007-07-18 16:29:46 +00:00
Evan Cheng 5184c9d787 Fix test. 
llvm-svn: 39976
 2007-07-17 18:16:09 +00:00
Evan Cheng 9ae2eb43d8 Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Dale Johannesen 2182f06f2d Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Evan Cheng ade8183fe8 Add test case for PR1545. 
llvm-svn: 39749
 2007-07-11 19:29:05 +00:00
Dan Gohman 60d6f96da3 Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for 
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.

llvm-svn: 38503
 2007-07-10 18:20:44 +00:00
Dan Gohman 4bd45b3d53 Add a regression test for folding spill code into scalar min and max. 
llvm-svn: 38492
 2007-07-10 15:34:29 +00:00
Chris Lattner 318ff8dd94 force a cpu without SSE 
llvm-svn: 38466
 2007-07-09 17:35:18 +00:00
Chris Lattner 0937478073 allow this to work on ppc-darwin 
llvm-svn: 38465
 2007-07-09 17:32:28 +00:00
Bill Wendling 3053244b27 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.

llvm-svn: 37863
 2007-07-04 00:19:54 +00:00
Dale Johannesen a8bf39ee31 New testcases for rev 37847 (PR's 1489 and 1505). 
llvm-svn: 37848
 2007-07-03 00:58:37 +00:00
Dan Gohman 9ff9908413 Add a basic test-case for passing and returning <4 x double> and 
<8 x float> values on X86.

llvm-svn: 37845
 2007-07-02 16:23:47 +00:00
Dan Gohman 11a4008a59 New test case. DAGCombiner should be able to fold -sin(-x) 
in -enable-unsafe-fp-math mode.

llvm-svn: 37841
 2007-07-02 15:43:20 +00:00
Evan Cheng d21e3ab873 New test. 
llvm-svn: 37823
 2007-06-29 23:17:15 +00:00
Evan Cheng 62acd01275 New test. 
llvm-svn: 37815
 2007-06-29 21:40:30 +00:00