2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
301f45cf6f
Fix a problem Nate and Duraid reported where simplifying nodes can cause
...
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.
llvm-svn: 26291
2006-02-20 06:51:04 +00:00
486d1bc5ed
Fix a problem on itanium with memset. The value to set has been promoted to
...
i64 before this code, so zero_ext doesn't work.
llvm-svn: 26290
2006-02-20 06:38:35 +00:00
abac61603f
Add checks to make sure we don't create bogus extend nodes, and fix a bug
...
where we were doing exactly that which was causing failures on x86 and
alpha.
llvm-svn: 26284
2006-02-18 02:40:58 +00:00
375e1a71cc
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
...
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
llvm-svn: 26269
2006-02-17 21:58:01 +00:00
fb5dbadf15
Clean up DemandedBitsAreZero interface
...
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
llvm-svn: 26263
2006-02-17 19:54:08 +00:00
57b3567552
Don't expand sdiv by power of two before legalize, since it will likely
...
generate illegal nodes.
llvm-svn: 26261
2006-02-17 07:26:20 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
9ec392b2aa
Fix another miscompilation exposed by lencode, where we lowered i64->f32
...
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
llvm-svn: 26254
2006-02-17 04:32:33 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
471627c49d
Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written
...
by Nate, I'm just committing it for him.
llvm-svn: 26230
2006-02-16 08:02:36 +00:00
93e4865d4b
Remove an unused function parameter.
...
llvm-svn: 26221
2006-02-15 22:12:35 +00:00
6781b6e62e
Turn a memcpy from string constant into a series of stores of constant values.
...
llvm-svn: 26219
2006-02-15 21:59:04 +00:00
2eea436192
Should not combine ISD::LOCATIONs until we have scheme to remove from
...
MachineDebugInfo tables.
llvm-svn: 26216
2006-02-15 19:34:44 +00:00
e2038bdeee
Lower memcpy with small constant size operand into a series of load / store
...
ops.
llvm-svn: 26195
2006-02-15 01:54:51 +00:00
0451499b3c
Doh again!
...
llvm-svn: 26188
2006-02-14 23:05:54 +00:00
ebb50a61d2
Using wrong DW_FORM.
...
llvm-svn: 26184
2006-02-14 22:01:57 +00:00
db2a7a736a
Keep to < 80 cols
...
llvm-svn: 26177
2006-02-14 20:12:38 +00:00
038521ef76
Missed a break so memcpy cases fell through to memset. Doh.
...
llvm-svn: 26176
2006-02-14 19:45:56 +00:00
d502610604
Fixed a build breakage.
...
llvm-svn: 26175
2006-02-14 09:11:59 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
81fcea8aa2
Expand memset dst, c, size to a series of stores if size falls below the
...
target specific theshold, e.g. 16 for x86.
llvm-svn: 26171
2006-02-14 08:22:34 +00:00
1784a9d267
now that libcalls don't suck, we can remove this hack
...
llvm-svn: 26164
2006-02-14 05:39:35 +00:00
8e2ee7358f
Fix a latent bug in the call sequence handling stuff. Some targets (e.g. x86)
...
create these nodes with flag results. Remember that we legalized them.
llvm-svn: 26156
2006-02-14 00:55:02 +00:00
390c63e9d9
Rename to better reflect usage (current and planned.)
...
llvm-svn: 26145
2006-02-13 12:50:39 +00:00
462505fc5f
Completely rewrite libcall insertion by the legalizer, providing the
...
following handy-dandy properties:
1. it is always correct now
2. it is much faster than before
3. it is easier to understand
This implementation builds off of the recent simplifications of the
legalizer that made it single-pass instead of iterative.
This fixes JM/lencod, JM/ldecod, and
CodeGen/Generic/2006-02-12-InsertLibcall.ll (at least on PPC).
llvm-svn: 26144
2006-02-13 09:18:02 +00:00
5995d0160c
Reorg for integration with gcc4. Old style debug info will not be passed though
...
to SelIDAG.
llvm-svn: 26115
2006-02-11 01:01:30 +00:00
a1ef3ec5b5
Added SelectionDAG::InsertISelMapEntry(). This is used to workaround the gcc
...
problem where it inline the map insertion call too aggressively. Before this
change it was producing a frame size of 24k for Select_store(), now it's down
to 10k (by calling this method rather than calling the map insertion operator).
llvm-svn: 26094
2006-02-09 22:11:03 +00:00
d3f1db93c1
More changes to reduce frame size.
...
Move all getTargetNode() out of SelectionDAG.h into SelectionDAG.cpp. This
prevents them from being inlined.
Change getTargetNode() so they return SDNode * instead of SDOperand to prevent
copying. It should also help compilation speed.
llvm-svn: 26083
2006-02-09 07:15:23 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
ba97264e72
rename fields of constant pool entries
...
llvm-svn: 26076
2006-02-09 04:22:52 +00:00
47f7319f00
Simplify code, alignment must be specified now.
...
llvm-svn: 26074
2006-02-09 02:26:04 +00:00
4576bb74d5
Make MachineConstantPool entries alignments explicit
...
llvm-svn: 26071
2006-02-09 02:23:13 +00:00
ed87dcd45f
Add support for assembler directives that wrap inline asm
...
llvm-svn: 26065
2006-02-08 23:41:56 +00:00
a10e23c19f
Compile this:
...
xori r6, r2, 1
rlwinm r6, r6, 0, 31, 31
cmpwi cr0, r6, 0
bne cr0, LBB1_3 ; endif
to this:
rlwinm r6, r2, 0, 31, 31
cmpwi cr0, r6, 0
beq cr0, LBB1_3 ; endif
llvm-svn: 26047
2006-02-08 02:13:15 +00:00
34f74c180a
Add support for modifier characters to operand printers
...
llvm-svn: 26021
2006-02-06 22:17:23 +00:00
0458fb76fd
Goodbye nasty macro.
...
llvm-svn: 26019
2006-02-06 21:54:05 +00:00
b643ff5546
Edit requests from Sabre.
...
llvm-svn: 26018
2006-02-06 19:12:02 +00:00
85263234a8
Changing model for the construction of debug information.
...
llvm-svn: 26016
2006-02-06 15:33:21 +00:00
8c9cd461df
Back out previous commit, it isn't safe.
...
llvm-svn: 26006
2006-02-05 08:23:00 +00:00
3dc8b89493
fold c1 << (x + c2) into (c1 << c2) << x. fix a warning.
...
llvm-svn: 26005
2006-02-05 08:07:24 +00:00
c89fdf1eb3
Handle urem by shifted powers of 2.
...
llvm-svn: 26001
2006-02-05 07:36:48 +00:00
25d178bece
handle combining A / (B << N) into A >>u (log2(B)+N) when B is a power of 2
...
llvm-svn: 26000
2006-02-05 07:20:23 +00:00
d37645c07d
* Added SDNode::isOnlyUse().
...
* Fix hasNUsesOfValue(), it should be const.
llvm-svn: 25990
2006-02-05 06:29:23 +00:00
cbab28414e
make sure that global doubles are aligned to 8 bytes
...
llvm-svn: 25981
2006-02-05 01:46:49 +00:00
a9b2525d3e
Implement the AsmPrinter::getPreferredAlignmentLog method.
...
llvm-svn: 25978
2006-02-05 01:29:18 +00:00
95ae171d5b
Fix VC++ warning.
...
llvm-svn: 25975
2006-02-04 16:20:31 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
57a004abfe
Fix VC++ warning.
...
llvm-svn: 25957
2006-02-04 03:27:39 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
65ad53feb3
Initial early support for non-register operands, like immediates
...
llvm-svn: 25952
2006-02-04 02:16:44 +00:00
c93403a7fb
Handle another case exposed on X86.
...
llvm-svn: 25949
2006-02-03 23:50:46 +00:00
71d20c4e18
Fix a nasty problem on two-address machines in the following situation:
...
store EAX -> [ss#0]
[ss#0] += 1
...
use(EAX)
In this case, it is not valid to rewrite this as:
store EAX -> [ss#0]
EAX += 1
store EAX -> [ss#0] ;;; this would also delete the store above
...
use(EAX)
... because EAX is not a dead at that point. Keep track of which registers
we are allowed to clobber, and which ones we aren't, and don't clobber the
ones we're not supposed to. :)
This should resolve the issues on X86 last night.
llvm-svn: 25948
2006-02-03 23:28:46 +00:00
507a3a7bd1
significantly simplify the VirtRegMap code by pulling the SpillSlotsAvailable
...
and PhysRegsAvailable maps out into a new AvailableSpills struct. No
functionality change.
This paves the way for a bugfix, coming up next.
llvm-svn: 25947
2006-02-03 23:13:58 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
f68fd20286
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
...
llvm-svn: 25941
2006-02-03 20:13:59 +00:00
6091407783
remove dead fn
...
llvm-svn: 25935
2006-02-03 06:51:34 +00:00
22e251abf1
Add common code for reassociating ops in the dag combiner
...
llvm-svn: 25934
2006-02-03 06:46:56 +00:00
3276ff7ac6
Fix VC++ compilation error caused by using a std::map iterator variable to receive
...
a std::multimap iterator value. For some reason, GCC doesn't have a problem with this.
llvm-svn: 25927
2006-02-03 03:48:54 +00:00
e18ef0d4a6
Remove move copies and dead stuff by not clobbering the result reg of a noop copy.
...
llvm-svn: 25926
2006-02-03 03:16:14 +00:00
774d4a190b
Simplify some code
...
llvm-svn: 25924
2006-02-03 03:06:49 +00:00
1ef239afb4
Add code that checks for noop copies, which triggers when either:
...
1. a target doesn't know how to fold load/stores into copies, or
2. the spiller rewrites the input to a copy to the same register as the dest
instead of to the reloaded reg.
This will be moved/improved in the near future, but allows elimination of
some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and
163 copies from 252.eon.
llvm-svn: 25922
2006-02-03 02:02:59 +00:00
02b5b9cdd6
Added case HANDLENODE to getOperationName().
...
llvm-svn: 25920
2006-02-03 01:33:01 +00:00
b7f24de4c8
Physregs may hold multiple stack slot values at the same time. Keep track
...
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 00:36:31 +00:00
f3aef1b004
Fix a deficiency in the spiller that Evan noticed. In particular, consider
...
this code:
store [stack slot #0 ], R10
= add R14, [stack slot #0 ]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1 , and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3 .
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-02 23:29:36 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
49beaf40fc
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
...
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
llvm-svn: 25901
2006-02-02 07:17:31 +00:00
49ce35542f
add two dag combines:
...
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
llvm-svn: 25898
2006-02-02 06:36:13 +00:00
0bd74558ae
make -debug output less newliney
...
llvm-svn: 25895
2006-02-02 00:38:08 +00:00
7f5880b1c7
Implement matching constraints. We can now say things like this:
...
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 00:25:23 +00:00
aa23fa9f43
Implement smart printing of inline asm strings, handling variants and
...
substituted operands. For this testcase:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
we now emit:
_test:
or r2, r3, r3
or r3, r4, r4
xyz r2, r2, r3 ;; look here
or r3, r2, r2
blr
... note the substituted operands. :)
llvm-svn: 25886
2006-02-01 22:41:11 +00:00
01bd9d9911
*** empty log message ***
...
llvm-svn: 25879
2006-02-01 19:05:15 +00:00
1558fc64f9
Implement simple register assignment for inline asms. This allows us to compile:
...
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-01 18:59:47 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3a5ed55187
adjust to changes in InlineAsm interface. Fix a few minor bugs.
...
llvm-svn: 25865
2006-02-01 01:28:23 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
2443ab932d
Allow custom lowering of fabs. I forgot to check in this change which
...
caused several test failures.
llvm-svn: 25852
2006-01-31 18:14:25 +00:00
e9721b2984
Only insert an AND when converting from BR_COND to BRCC if needed.
...
llvm-svn: 25832
2006-01-31 05:04:52 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
57ecb561c6
Print the most trivial inline asms.
...
llvm-svn: 25822
2006-01-30 23:00:08 +00:00
f263a23735
Fix a bug in my legalizer reworking that caused the X86 backend to not get
...
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll
llvm-svn: 25821
2006-01-30 22:43:50 +00:00
d6f5ae4455
don't insert an and node if it isn't needed here, this can prevent folding
...
of lowered target nodes.
llvm-svn: 25804
2006-01-30 04:22:28 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
3b40e64aa3
pass the address of MaskedValueIsZero into isMaskedValueZeroForTargetNode,
...
to permit recursion
llvm-svn: 25799
2006-01-30 03:49:37 +00:00
4d1ea71a31
Fix RET of promoted values on targets that custom expand RET to a target node.
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llvm-svn: 25794
2006-01-29 21:02:23 +00:00
2c748afd6c
cleanups to the ValueTypeActions interface
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llvm-svn: 25785
2006-01-29 08:42:06 +00:00
ccb4476c87
Remove some special case hacks for CALLSEQ_*, using UpdateNodeOperands
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instead.
llvm-svn: 25780
2006-01-29 07:58:15 +00:00
2f292789dc
Allow custom expansion of ConstantVec nodes. PPC will use this in the future.
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llvm-svn: 25774
2006-01-29 06:34:16 +00:00
758b0ac54b
Legalize ConstantFP into TargetConstantFP when the target allows. Implement
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custom expansion of ConstantFP nodes.
llvm-svn: 25772
2006-01-29 06:26:56 +00:00
678da98835
eliminate uses of SelectionDAG::getBR2Way_CC
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llvm-svn: 25767
2006-01-29 06:00:45 +00:00
d02b05473c
Use the new "UpdateNodeOperands" method to simplify LegalizeDAG and make it
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faster. This cuts about 120 lines of code out of the legalizer (mostly code
checking to see if operands have changed).
It also fixes an ugly performance issue, where the legalizer cloned the entire
graph after any change. Now the "UpdateNodeOperands" method gives it a chance
to reuse nodes if the operands of a node change but not its opcode or valuetypes.
This speeds up instruction selection time on kimwitu++ by about 8.2% with a
release build.
llvm-svn: 25746
2006-01-28 10:58:55 +00:00
580b12ad34
add another method variant
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llvm-svn: 25744
2006-01-28 10:09:25 +00:00
f34156e8cb
add some methods for updating nodes
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llvm-svn: 25742
2006-01-28 09:32:45 +00:00
eb63751499
minor tweaks
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llvm-svn: 25740
2006-01-28 08:31:04 +00:00
689bdcc9cf
move a bunch of code, no other change.
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llvm-svn: 25739
2006-01-28 08:25:58 +00:00
fcfda5a174
remove a couple more now-extraneous legalizeop's
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llvm-svn: 25738
2006-01-28 08:22:56 +00:00
364b89a784
fix a bug
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llvm-svn: 25737
2006-01-28 07:42:08 +00:00
9dcce6da8e
Several major changes:
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1. Pull out the expand cases for BSWAP and CT* into a separate function,
reducing the size of LegalizeOp.
2. Fix a bug where expand(bswap i64) was wrong when i64 is legal.
3. Changed LegalizeOp/PromoteOp so that the legalizer never needs to be
iterative. It now operates in a single pass over the nodes.
4. Simplify a LOT of code, with a net reduction of ~280 lines.
llvm-svn: 25736
2006-01-28 07:39:30 +00:00
fd4a7f76a9
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
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relegalizes the stuff it returns.
Add the ability to custom expand ADD/SUB, so that targets don't need to deal
with ADD_PARTS/SUB_PARTS if they don't want.
Fix some obscure potential bugs and simplify code.
llvm-svn: 25732
2006-01-28 05:07:51 +00:00
10f677508f
Instead of making callers of ExpandLibCall legalize the result, make
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ExpandLibCall do it itself.
llvm-svn: 25731
2006-01-28 04:28:26 +00:00
a593acfe66
Eliminate the need to do another iteration of the legalizer after inserting
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a libcall.
llvm-svn: 25730
2006-01-28 04:23:12 +00:00
98ed05c81d
remove method I just added
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llvm-svn: 25728
2006-01-28 03:43:09 +00:00
43b867dd3b
add a new callback
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llvm-svn: 25727
2006-01-28 03:37:03 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
af397cec0b
Add a missing case to the dag combiner.
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llvm-svn: 25723
2006-01-28 01:06:30 +00:00
fb16a62fba
Remove the ISD::CALL and ISD::TAILCALL nodes
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llvm-svn: 25721
2006-01-28 00:18:58 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
0cda006a69
Using bit size of integers instead of ambiguous "long" et all.
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llvm-svn: 25694
2006-01-27 20:31:25 +00:00
4a84e97421
Sorry - really folowing convention.
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llvm-svn: 25691
2006-01-27 18:32:41 +00:00
116bb15473
Following convention.
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llvm-svn: 25689
2006-01-27 18:28:31 +00:00
fc3eca9023
fix build
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llvm-svn: 25687
2006-01-27 18:16:17 +00:00
ecd7e61a1f
Fix build error that is apparently only a warning with some compilers.
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llvm-svn: 25686
2006-01-27 17:31:30 +00:00
2b6efa9d41
Forgot the version number.
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llvm-svn: 25685
2006-01-27 15:46:54 +00:00
f98fc8441c
Improve visibility/correctness of operand indices in "llvm.db" objects.
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Handle 64 in DIEs.
llvm-svn: 25684
2006-01-27 15:20:54 +00:00
061d9e2cf0
Stub out a method
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llvm-svn: 25676
2006-01-27 02:10:10 +00:00
4df279cfda
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
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ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
476e67be14
initial selectiondag support for new INLINEASM node. Note that inline asms
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with outputs or inputs are not supported yet. :)
llvm-svn: 25664
2006-01-26 22:24:51 +00:00
0689dfad23
Use global information to fill out Dwarf compile units.
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llvm-svn: 25662
2006-01-26 21:22:49 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
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Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
c4c339c3d0
Clean up some code; improve efficiency; and fixed a potential bug involving
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chain successors.
llvm-svn: 25630
2006-01-26 00:30:29 +00:00
5edde66863
Don't break the optimized build (by incorrect placement of #endif)
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llvm-svn: 25613
2006-01-25 21:49:13 +00:00
1880f8db02
No need to keep track of top and bottom nodes in a group since the vector is
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already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
e74795cd70
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
c3cafb8a67
Make it even more portable.
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llvm-svn: 25605
2006-01-25 17:18:50 +00:00
fb20616aa6
Fix VC++ compilation error.
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llvm-svn: 25604
2006-01-25 17:17:49 +00:00
ab49556cf4
Bottom up register usage reducing list scheduler.
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llvm-svn: 25601
2006-01-25 09:14:32 +00:00
fbc88a624a
Keep track of bottom / top element of a set of flagged nodes.
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llvm-svn: 25600
2006-01-25 09:13:41 +00:00
a6eff8a432
If scheduler choice is the default (-sched=default), use target scheduling
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preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
llvm-svn: 25599
2006-01-25 09:12:57 +00:00
a292744ecc
Portably cast a pointer to an integer.
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llvm-svn: 25594
2006-01-25 02:40:10 +00:00
1dbc389ad2
fix build on 64 bit hosts
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llvm-svn: 25591
2006-01-24 21:26:43 +00:00
f9a1e3aadc
Fix an infinite loop I caused by making sure to legalize the flag operand
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of CALLSEQ_* nodes
llvm-svn: 25582
2006-01-24 05:48:21 +00:00
12f8441c03
Fix VC++ compilation error.
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llvm-svn: 25577
2006-01-24 04:43:17 +00:00
b56a80061a
Remove unused variables.
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llvm-svn: 25576
2006-01-24 04:42:53 +00:00
00fcdfef0d
rename method
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llvm-svn: 25572
2006-01-24 04:16:34 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
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llvm-svn: 25569
2006-01-24 00:49:18 +00:00
e3a79268a2
Print file-scope inline asm blocks at the start of the output file.
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llvm-svn: 25565
2006-01-23 23:47:53 +00:00
683352382e
another couple selects
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llvm-svn: 25551
2006-01-23 21:51:14 +00:00
c28563874c
another selectto
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llvm-svn: 25548
2006-01-23 20:59:12 +00:00
b8566fa10a
Typo.
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llvm-svn: 25545
2006-01-23 13:34:04 +00:00
31272347d4
Skeleton of the list schedule.
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llvm-svn: 25544
2006-01-23 08:26:10 +00:00
421cfe8006
Minor clean up.
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llvm-svn: 25543
2006-01-23 08:25:34 +00:00
763dfd7723
Fix Regression/CodeGen/SparcV8/2006-01-22-BitConvertLegalize.ll by making
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sure that the result of expanding a BIT_CONVERT node is itself legalized.
llvm-svn: 25538
2006-01-23 07:30:46 +00:00
87063b9986
Remove a couple of unnecessary #include's
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llvm-svn: 25535
2006-01-23 07:21:01 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
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llvm-svn: 25532
2006-01-23 07:01:07 +00:00
deda32a786
Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on
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PPC.
llvm-svn: 25522
2006-01-23 05:22:07 +00:00
Jim Laskey