da1b152c43
Make this work for FP constantexprs
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llvm-svn: 23773
2005-10-17 20:18:38 +00:00
7fde91e365
Oops, X+0.0 isn't foldable, but X+-0.0 is.
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llvm-svn: 23772
2005-10-17 17:56:38 +00:00
32979336a7
relax this a bit, as we only support the default rounding mode
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llvm-svn: 23771
2005-10-17 17:49:32 +00:00
8113c67003
Apparently, people object to floating pointers. Picky picky.
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llvm-svn: 23770
2005-10-17 15:19:24 +00:00
87ce5d85bb
As requested, a blurb on sub-targets.
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llvm-svn: 23769
2005-10-17 12:19:10 +00:00
721f3ce90f
fix some grammar-o's I noticed
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llvm-svn: 23768
2005-10-17 04:18:41 +00:00
9fcf000d9e
Feedback from Nate.
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llvm-svn: 23767
2005-10-17 03:09:31 +00:00
776c73f032
Document -view-isel-dags and -view-sched-dags
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llvm-svn: 23766
2005-10-17 01:40:33 +00:00
ed54f2f5e7
Add notes about MF.viewCFG() and friends.
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llvm-svn: 23765
2005-10-17 01:36:23 +00:00
eeb2bda2fa
add a trivial fold
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llvm-svn: 23764
2005-10-17 01:07:11 +00:00
17acad625c
Add a bunch of info about the isel autogenerator. Review appreciated!
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llvm-svn: 23763
2005-10-16 20:02:19 +00:00
d6f1a33d26
Fill this out some more. Add description of MBB/MF. Fix some broken links,
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turn some broken <a name> into <a href>'s.
llvm-svn: 23762
2005-10-16 18:31:08 +00:00
c9afa28b92
Add a stub for the TargetSubtarget class. Jim, please fill a blurb in here
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when you get a chance.
llvm-svn: 23761
2005-10-16 17:06:07 +00:00
bf589c5129
Update this significantly, mention subtarget and isel generation support.
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llvm-svn: 23760
2005-10-16 17:03:22 +00:00
6cca84e43c
More PPC32 -> PPC changes, as well as merging some classes that were
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redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
825298b060
Make the generated code significantly more memory efficient, by using
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SelectNodeTo instead of getTargetNode when possible.
llvm-svn: 23758
2005-10-16 01:41:58 +00:00
acf3d627b9
update this a little bit to talk about the dag combiner and remove inaccuracies.
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This still doesn't talk about autogen much
llvm-svn: 23757
2005-10-16 00:36:38 +00:00
e540800d5a
Fix this logic.
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llvm-svn: 23756
2005-10-15 22:35:40 +00:00
17cc9edd33
Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll:test3
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llvm-svn: 23755
2005-10-15 22:18:08 +00:00
c0896117d3
Remove some dead code now that the dag combiner exists.
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llvm-svn: 23754
2005-10-15 22:08:02 +00:00
d869bec4fe
Remove some dead code: the ORI/ORIS cases are autogen'd. This makes
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SelectIntImmediateExpr dead.
llvm-svn: 23753
2005-10-15 22:06:18 +00:00
03354280eb
prune #includes
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llvm-svn: 23752
2005-10-15 21:58:54 +00:00
a52969c8d6
These instructions are now autogenerated
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llvm-svn: 23751
2005-10-15 21:44:56 +00:00
286c1d7cfa
Add a pattern for FSQRTS
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llvm-svn: 23750
2005-10-15 21:44:15 +00:00
efa382616b
remove dead code
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llvm-svn: 23749
2005-10-15 21:40:12 +00:00
6b22d2554a
Implement the last major missing piece in the DAG isel generator: when emitting
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a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction. This allows FMA32
patterns to not match double expressions for example.
llvm-svn: 23748
2005-10-15 21:34:21 +00:00
b986f471be
Use getExtLoad here instead of getNode, as extloads produce two values. This
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fixes a legalize failure on SPASS for itanium.
llvm-svn: 23747
2005-10-15 20:24:07 +00:00
e33870d154
remove broken SRA/rlwimi case
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llvm-svn: 23746
2005-10-15 19:04:48 +00:00
6f3b954662
Rename PPC32*.h to PPC*.h
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This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00
0aa794ba5b
Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo
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and PPC32JITInfo classes should be merged.
llvm-svn: 23744
2005-10-14 23:53:41 +00:00
bfca1ab79d
Rename PowerPC*.h to PPC*.h
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llvm-svn: 23743
2005-10-14 23:51:18 +00:00
e80bf1b33a
Rename PowerPCInstrBuilder.h -> PPC*
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llvm-svn: 23742
2005-10-14 23:45:43 +00:00
2ed745a905
Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine
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still should be merged into the PPC32TargetMachine class
llvm-svn: 23741
2005-10-14 23:44:05 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
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llvm-svn: 23740
2005-10-14 23:40:39 +00:00
f3b97f53b9
These are dead
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llvm-svn: 23739
2005-10-14 23:38:51 +00:00
0921e3bfc1
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
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llvm-svn: 23738
2005-10-14 23:37:35 +00:00
09cd9e7661
Like the comment says...
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llvm-svn: 23737
2005-10-14 22:48:24 +00:00
2121f3ca50
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
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from the .td file that correspond to it
llvm-svn: 23736
2005-10-14 22:44:13 +00:00
9d7008b08d
Properly split f32 and f64 into separate register classes for scalar sse fp
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fixing a bunch of nasty hackery
llvm-svn: 23735
2005-10-14 22:06:00 +00:00
c41e1be2e8
Remove an unnecsesary file. PPC32 and PPC64 share architected registers.
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We will decide with subtarget support whether we ever use an i64 register
class.
llvm-svn: 23734
2005-10-14 18:58:46 +00:00
56f31f5408
add the integer truncate/extension operations
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llvm-svn: 23733
2005-10-14 06:40:20 +00:00
95866d3923
Make sure targets depend on TargetSelectionDAG.td
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llvm-svn: 23732
2005-10-14 06:31:58 +00:00
7d9f719d42
These are now autogenerated
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llvm-svn: 23731
2005-10-14 06:26:29 +00:00
c4db8f4163
Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
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type constraint. This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.
llvm-svn: 23730
2005-10-14 06:25:00 +00:00
ecaf56b21a
Fairly serious rework of the typing code to add new int/fp lattice values.
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Overall, no functionality change yet though.
llvm-svn: 23729
2005-10-14 06:12:03 +00:00
cdf483556f
simplify the code a bit
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llvm-svn: 23728
2005-10-14 05:08:37 +00:00
9c0d3c5932
Add patterns for FP round/extend
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llvm-svn: 23727
2005-10-14 04:55:50 +00:00
6e83cbf7f3
add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it
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llvm-svn: 23726
2005-10-14 04:55:10 +00:00
4892df38f3
Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint
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llvm-svn: 23725
2005-10-14 04:53:53 +00:00
7b0275ba8c
Implement a couple of new (important) features.
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1. If an operation has to be int or fp and the target only supports one
int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
for patterns involving those operators, since we do not emit the code to
check for them yet. This prevents PPC from generating FP ops currently.
Also move some code around into more logical places.
llvm-svn: 23724
2005-10-14 04:11:13 +00:00
Chris Lattner