predefines based on the output of GCC as well as the CPU predefines.
Invert tests for __AVX__, Clang's AVX feature is hard coded off still.
Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's
documentation, and ICC's documentation (such as I could dig up).
Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and
nothing (resp.).
llvm-svn: 140692
automate the process of updating and generating these tests.
If anyone is really interested, I can check my scripts for generating
this test in, but its a horrible pile of shell... Not sure its really
worth it.
llvm-svn: 140691
fallthrough now that we're working with a switch. Also remove a dubious
"feature" regarding k6 processors and 3dnow and leave a fixme... Not
that anyone is likely to care about correct tuning for k6 processors
with and w/o 3dnow...
llvm-svn: 140687
selected CPU model to the enumeration. This parses the string
representation once using a StringSwitch on SetCPU. It returns an error
for strings which are not recognized (yay!). Finally it replaces
ridiculous if-chains with switches that cover all enumerators.
The last change required adding several missing entries to the features
function. These were obvious on inspection. Yay for a pattern that gives
warnings when we miss one.
No new test cases yet, as I want to get the 64-bit errors working first.
I'll then start fleshing out the testing more. Currently I'm primarily
testing on Linux, but I'm hoping check whether there are interesting
differences on darwin before long...
llvm-svn: 140685
it an error if a CPU is provided for a target that doesn't implement
logic handling CPU settings, to match the ABI settings. It also removes
the CPU parameter from the getDefaultFeatures method. This parameter was
always filled in with the same value as setCPU was called with, and at
this point every single target implementation that referenced the CPU
within this function has needed to store the CPU via setCPU anyways in
order to implement other interface points.
llvm-svn: 140683
This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
llvm-svn: 140676
The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
llvm-svn: 140675
is *very* much a WIP that I'll be refining over the next several
commits, but I need to get this checkpoint in place for sanity.
This also adds a much more comprehensive test for architecture macros,
which is roughly generated by inspecting the behavior of a trunk build
of GCC. It still requires some massaging, but eventually I'll even check
in the script that generates these so that others can use it to append
more tests for more architectures, etc.
Next up is a bunch of simplification of the Targets.cpp code, followed
by a lot more test cases once we can reject invalid architectures.
llvm-svn: 140673
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
In particular, it iterates through the executable module's SBSections, looking for the
'__TEXT' section and further iterates on its subsections (of SBSection type, too).
llvm-svn: 140654
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
attribute must match its overriden method. Same also for
ns_returns_retained/not_retained on the result type.
This is one half of // rdar://10187884
llvm-svn: 140649
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
NAKAMURA Takumi