698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
...
logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
a237bdbe52
FileCheckize this in a hope to quiet a valgrind warning on grep.
...
llvm-svn: 116376
2010-10-12 23:47:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
...
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
...
llvm-svn: 116354
2010-10-12 22:24:10 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
65eb03ed6b
Add a simple testcase for tbaa.
...
llvm-svn: 116272
2010-10-11 23:54:13 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
3e02306fed
PR8297
...
llvm-svn: 116223
2010-10-11 21:08:42 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
...
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
6002b3b3e1
Remove now non-existent option.
...
llvm-svn: 116219
2010-10-11 20:21:21 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
f8f7537a77
force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.
...
llvm-svn: 116170
2010-10-10 18:59:01 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
...
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
...
llvm-svn: 116158
2010-10-09 22:06:36 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
b20b08f898
Don't test a removed function.
...
llvm-svn: 116154
2010-10-09 15:53:25 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
748265b0da
Simplify test and move into a generic "crash" ll file.
...
llvm-svn: 116130
2010-10-09 00:29:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
3e210eb398
testcase that goes with r116053
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llvm-svn: 116054
2010-10-08 05:12:30 +00:00
8ed76f87cf
rename test
...
llvm-svn: 116052
2010-10-08 05:05:06 +00:00
420cf26d99
merge tests
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llvm-svn: 116051
2010-10-08 05:04:58 +00:00
6a8a65cb43
filecheckize.
...
llvm-svn: 116050
2010-10-08 05:02:29 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
00ee155b25
Fix Formatting.
...
llvm-svn: 116038
2010-10-08 03:17:21 +00:00
8eb636e5de
MC-COFF: Fix Simple and Complex type. Fixes PR8320.
...
llvm-svn: 116037
2010-10-08 03:17:11 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
42a07e8545
Add test file for simple ARM binary encodings with MC
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llvm-svn: 116024
2010-10-08 00:47:59 +00:00
00be34d009
MC-COFF: Add test for my last commit.
...
llvm-svn: 116015
2010-10-08 00:00:28 +00:00
57da4caa85
Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.
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llvm-svn: 116004
2010-10-07 23:29:37 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
efc22274cd
test: Fix binary stdin issues with coff-dump on Windows.
...
llvm-svn: 115908
2010-10-07 06:29:21 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
805b74d650
rename add some comments.
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llvm-svn: 115741
2010-10-06 04:37:17 +00:00
7d5bb96723
filecheckize
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llvm-svn: 115740
2010-10-06 04:36:30 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
10a0fdeab5
PSHUFW is in SSE, not SSSE3.
...
llvm-svn: 115691
2010-10-05 21:58:12 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
8ccdd25fbd
test/COFF: Fix symbol indexes and names. Update tests to match.
...
llvm-svn: 115642
2010-10-05 17:57:08 +00:00
f6230d1d4b
test/COFF: Remove temp file usage.
...
llvm-svn: 115641
2010-10-05 17:56:56 +00:00
e58f37f74d
test/coff-dump: Support reading from stdin.
...
llvm-svn: 115640
2010-10-05 17:56:46 +00:00
868aaf3c3d
Cleanup Whitespace.
...
llvm-svn: 115639
2010-10-05 17:56:37 +00:00
d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
...
having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
...
llvm-svn: 115623
2010-10-05 15:48:37 +00:00
259bcdad06
Tests that now pass.
...
llvm-svn: 115622
2010-10-05 15:43:32 +00:00
7681b41720
test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
...
llvm-svn: 115611
2010-10-05 11:16:24 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
...
llvm-svn: 115580
2010-10-05 00:21:40 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
fd1fff8b19
Implement ELF::R_X86_64_GOTPCREL.
...
llvm-svn: 115547
2010-10-04 19:51:39 +00:00
baadbd554a
Produce a R_X86_64_PLT32 when needed.
...
llvm-svn: 115541
2010-10-04 19:04:13 +00:00
b2c4ca6433
Produce a R_X86_64_GOT32 when needed.
...
llvm-svn: 115537
2010-10-04 18:44:25 +00:00
87f77b5f9a
Add hook in MCSection to decide when to use "optimized nops", for each
...
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
llvm-svn: 115523
2010-10-04 17:32:41 +00:00
da0e3d07b2
Include the section address in the computation of the relocation.
...
llvm-svn: 115509
2010-10-04 15:59:01 +00:00
7c48b06930
Correctly compute the relocation when it is not in the first fragment.
...
llvm-svn: 115506
2010-10-04 15:28:43 +00:00
d77a443631
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
Chris Lattner