Commit Graph

244573 Commits

Author SHA1 Message Date
Matt Arsenault 253640e18d AMDGPU: Assume spilling will occur at -O0
Because everything live is spilled at the end of a
block by fast regalloc, assume this will happen and
avoid the copies of the resource descriptor.

llvm-svn: 284119
2016-10-13 13:10:00 +00:00
Simon Pilgrim 26b6dbc369 Copy+pasts typo in comment describing combine test
Repeated the "fold (mul x, 0) -> 0" instead of "fold (mul x, 1) -> x"

llvm-svn: 284118
2016-10-13 12:54:32 +00:00
Simon Pilgrim fa8fadc0e5 [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A folding
llvm-svn: 284117
2016-10-13 12:49:31 +00:00
Matt Arsenault dac31db12f AMDGPU: Fix truncate to bool warnings
llvm-svn: 284116
2016-10-13 12:45:16 +00:00
Simon Dardis 515e8699f4 [mips] Add IAS support for dvp, evp
These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.

Reviewers: vkalintiris

Differential Review: https://reviews.llvm.org/D24291

llvm-svn: 284115
2016-10-13 12:12:56 +00:00
Richard Chamberlain a0c82e18d5 [lldb] Improve identification of Linux core dumps. Fix for bug #30485.
Summary:
ObjectFileELF::RefineModuleDetailsFromNote() identifies Linux core dumps by searching for
 library paths starting with /lib/x86_64-linux-gnu or /lib/i386-linux-gnu. This change widens the
test to allow for linux installations which have addition directories in the path.

Reviewers: ted, hhellyer, clayborg

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D25179

llvm-svn: 284114
2016-10-13 12:11:00 +00:00
Simon Pilgrim 833b8a2071 [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalization
Improves commutation potential

llvm-svn: 284113
2016-10-13 12:05:20 +00:00
Artem Dergachev bb51662d8d [analyzer] Link libStaticAnalyzerCheckers to libASTMatchers.
AST matchers are useful for the analyzer's checkers.
More patches on particular checkers shall follow.

This is the first time clang binary gets linked to ASTMatchers.
The binary size increase for the clang executable would be
+0.5% in release mode, +2% in debug mode.

Differential Revision: https://reviews.llvm.org/D25429

llvm-svn: 284112
2016-10-13 11:41:12 +00:00
Haojian Wu e77bcc7371 [clang-move] Better support enclosing class.
Summary:
* When moving an outermost enclosing class, all its nested classes should also
  be moved together.
* Add a test for not moving nested class.

Reviewers: ioeric

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25369

llvm-svn: 284111
2016-10-13 10:31:00 +00:00
Alexey Bataev 2f5ed34279 Fix for PR30639: CGDebugInfo Null dereference with OpenMP array
access, by Erich Keane

OpenMP creates a variable array type with a a null size-expr. The Debug
generation failed to due to this. This patch corrects the openmp
implementation, updates the tests, and adds a new one for this
condition.

Differential Revision: https://reviews.llvm.org/D25373

llvm-svn: 284110
2016-10-13 09:52:46 +00:00
Haojian Wu 9df3ac1f56 Recommit r283538 "[clang-move] Support moving multiple classes in one run."
llvm-svn: 284109
2016-10-13 08:48:42 +00:00
Oren Ben Simhon 92ccbf20ff [X86] Basic additions to support RegCall Calling Convention.
The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call.
This calling convention ensures that as many values as possible are passed or returned in registers.
This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86.

Differential Revision: http://reviews.llvm.org/D25022

llvm-svn: 284108
2016-10-13 07:53:43 +00:00
Daniel Jasper bee9dea306 Silence unused warning in non-assert builds.
llvm-svn: 284107
2016-10-13 06:39:44 +00:00
Craig Topper 3d41f91f61 [AVX-512] Fix v16i32 zero extending shuffle test case so it's really zero extend.
llvm-svn: 284106
2016-10-13 05:41:01 +00:00
Craig Topper ff23af4299 [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.
llvm-svn: 284105
2016-10-13 05:29:41 +00:00
Craig Topper 05242739c2 [AVX-512] Add tests for basic 512-bit zero extending shuffle patterns. Code will be improved in a future commit.
llvm-svn: 284104
2016-10-13 05:29:37 +00:00
Diana Picus acb444f58d Remove a FIXME that I forgot about. NFC.
Sorry about the noise.

llvm-svn: 284103
2016-10-13 05:28:55 +00:00
Craig Topper 8cb2efa58a [X86] Simplify the lowering code for extracting and inserting subvectors.
We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom.
We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width.

llvm-svn: 284102
2016-10-13 04:14:47 +00:00
Eric Fiselier 5e198da869 Revert r282345 - Use __attribute__((internal_linkage)) when available.
llvm-svn: 284101
2016-10-13 04:07:58 +00:00
Vadim Macagon bdff2dc8d7 Fix Python binding generation build step on Windows
Summary:
If Python is installed to a location that contains spaces
(e.g. "C:\Program Files\Python3") then the build fails while attempting
to run the modify-python-lldb.py script because the path to the Python
executable is not double-quoted before being passed to the shell. The
fix consists of letting Python handle the formatting of the command
line, since subprocess.Popen() is perfectly capable of handling paths
containing spaces if it's given the command and arguments as a list
instead of a single pre-formatted string.

Reviewers: zturner, clayborg

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D25396

llvm-svn: 284100
2016-10-13 04:07:22 +00:00
Sebastian Pop 5068d7a338 Memory-SSA: strengthen defClobbersUseOrDef interface
As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make
sure fences are properly handled.

llvm-svn: 284099
2016-10-13 03:23:33 +00:00
Sebastian Pop 5ba9f24ed7 commit back "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"
This is with an extra change to avoid calling MemoryLocation::get() on a call instruction.

Differential Revision: https://reviews.llvm.org/D25542

llvm-svn: 284098
2016-10-13 01:39:10 +00:00
Quentin Colombet 6b87a3109c [AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit load
This allows RegBankSelect in greedy mode to get rid some of the cross
register bank copies when loads are involved in the chain of
computation.

llvm-svn: 284097
2016-10-13 01:01:23 +00:00
Reid Kleckner 741d8a21d3 Correct PrivateLinkage for COFF
- Use storage class C_STAT for 'PrivateLinkage' The storage class for
  PrivateLinkage should equal to the Internal Linkage.

- Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes
  x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix
  "L" may conflict to the normal symbol name starting with 'L'.

Based on a patch by Han Sangjin! Manually updated test cases.

llvm-svn: 284096
2016-10-13 00:55:24 +00:00
Peter Collingbourne 3aa0a2510e Add "opt" to the list of test dependencies.
We've started using it in the ThinLTO tests.

Also remove a repeated dependency on llvm-nm.

llvm-svn: 284095
2016-10-13 00:49:21 +00:00
Quentin Colombet cd80e97e88 [AArch64][RegisterBankInfo] Provide alternative mappings for G_BITCASTs.
Thanks to this patch, RegBankSelect is able to get rid of some register
bank copies as demonstrated in the test case.

llvm-svn: 284094
2016-10-13 00:34:48 +00:00
Reid Kleckner 8958f6a529 Revert "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"
This CL didn't actually address the test case in PR30499, and clang
still crashes.

Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC"

Reverts r283965 and r283967.

llvm-svn: 284093
2016-10-13 00:18:26 +00:00
Rui Ueyama acb67bcb98 Move a utility function to Strings.cpp.
So that we can use the function from anywhere.

llvm-svn: 284092
2016-10-13 00:13:15 +00:00
Quentin Colombet 45c9c1432f [AArch64][RegisterBankInfo] Describe cross regbank copies statically.
NFC.

llvm-svn: 284091
2016-10-13 00:12:06 +00:00
Quentin Colombet 9e64919b7c [AArch64][RegisterBankInfo] Use static mapping for same bank G_BITCAST.
NFC.

llvm-svn: 284090
2016-10-13 00:12:04 +00:00
Quentin Colombet db643d9091 [AArch64][MachineLegalizer] Mark more G_BITCAST as legal.
Basically any vector types that fits in a 32-bit register is also valid
as far as copies are concerned.

llvm-svn: 284089
2016-10-13 00:12:01 +00:00
Quentin Colombet f760799c40 [AArch64][RegisterBankInfo] Bump the cost of vector loads.
This does not change anything yet, because we do not offer any
alternative mapping.

llvm-svn: 284088
2016-10-13 00:11:59 +00:00
Quentin Colombet f35a8c5bdc [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.
This does not change anything yet, because we do not offer any
alternative mapping.

llvm-svn: 284087
2016-10-13 00:11:57 +00:00
Quentin Colombet 27b40356f7 [AArch64][RegisterBankInfo] Provide more realistic copy costs.
llvm-svn: 284086
2016-10-13 00:11:55 +00:00
Albert Gutowski 3245ee7e57 fix function label name in addressofreturnaddress test
llvm-svn: 284085
2016-10-12 23:58:45 +00:00
Devin Coughlin 0bd37a1a36 [analyzer] DeallocChecker: Don't warn about directly-set IBOutlet ivars on macOS
On macOS (but not iOS), if an ObjC property has no setter, the nib-loading code
for an IBOutlet is documented as directly setting the backing ivar without
retaining the value -- even if the property is 'retain'.

This resulted in false positives from the DeallocChecker for code that did not
release such ivars in -dealloc.

To avoid these false positives, treat IBOutlet ivars that back a property
without a setter as having an unknown release requirement in macOS.

rdar://problem/28507353

llvm-svn: 284084
2016-10-12 23:57:05 +00:00
Albert Gutowski 1255c19656 fix ms-intrinsics labels code to work with builds with assertions
llvm-svn: 284083
2016-10-12 23:52:38 +00:00
Mehdi Amini c8d2a48d03 [GitHubMove Doc] Properly nest a subsection in the proposal
llvm-svn: 284082
2016-10-12 23:36:11 +00:00
Richard Smith 88d10b68e0 Revert r284008. This is us to fail to instantiate static data members in some
cases. I'm working on reducing a testcase.

llvm-svn: 284081
2016-10-12 23:29:02 +00:00
Yunzhong Gao d9fa56a4fb [NFC] Fixing the description for _mm_store_ps and _mm_store_ps1.
It seems that the doxygen description of these two intrinsics were swapped by
mistake.

llvm-svn: 284080
2016-10-12 23:27:27 +00:00
Rui Ueyama 5665af836f Fix variable name. NFC.
llvm-svn: 284079
2016-10-12 23:22:59 +00:00
Albert Gutowski 57ad5fe288 fix title underline length
llvm-svn: 284078
2016-10-12 23:10:02 +00:00
Mehdi Amini 647deb8f1a Moving to GitHub - Unified Proposal
This document describes the proposal to move to GitHub, and
compare the two proposals through various workflow examples,
presenting the current set of commands following by the ones
involved in each of the two proposals.

It is intended to supersede the previous "submodule proposal"
document entirely, and drive the discussion at the BoF during
the next Dev Meeting.

Differential Revision: https://reviews.llvm.org/D24167

llvm-svn: 284077
2016-10-12 23:02:02 +00:00
Krzysztof Parzyszek abc0662f04 Handle lane masks in LivePhysRegs when adding live-ins
Differential Revision: https://reviews.llvm.org/D25533

llvm-svn: 284076
2016-10-12 22:53:41 +00:00
Tim Northover fb8d989818 GlobalISel: support G_TRUNC selection on AArch64.
Ahmed's patch again.

llvm-svn: 284075
2016-10-12 22:49:15 +00:00
Tim Northover 69271c64d5 GlobalISel: support int <-> float conversions on AArch64.
More of Ahmed's work.

llvm-svn: 284074
2016-10-12 22:49:11 +00:00
Tim Northover 7dd378dd08 GlobalISel: select G_FCMP instructions on AArch64.
Another of Ahmed's patches.

llvm-svn: 284073
2016-10-12 22:49:07 +00:00
Tim Northover 6c02ad5e4f GlobalISel: support selection of G_ICMP on AArch64.
Patch from Ahmed Bougaca again.

llvm-svn: 284072
2016-10-12 22:49:04 +00:00
Tim Northover 5e3dbf326c GlobalISel: select G_BRCOND instructions on AArch64.
llvm-svn: 284071
2016-10-12 22:49:01 +00:00
Tim Northover 6aacd27cd7 GlobalISel: mark G_BRCOND on s1 as legal.
It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter.

llvm-svn: 284070
2016-10-12 22:48:36 +00:00