fa0df55bdd
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
...
Thanks for the suggestions Bill :-)
llvm-svn: 43742
2007-11-05 23:12:20 +00:00
419b6d7ce4
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
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and by restructuring the X86 version.
New I just have to move this to a common place :-)
llvm-svn: 43554
2007-10-31 14:39:58 +00:00
063f177300
Make ARM an X86 memcpy expansion more similar to each other.
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Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
llvm-svn: 43552
2007-10-31 11:52:06 +00:00
1f2dd35898
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
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llvm-svn: 43234
2007-10-22 22:11:27 +00:00
18a831d783
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
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llvm-svn: 43176
2007-10-19 14:35:17 +00:00
84f3461c49
legalizing the ret operation on f64 shouldn't introduce a new
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i64 bit convert needlessly.
llvm-svn: 43116
2007-10-18 06:17:07 +00:00
482732af9d
Set ISD::FPOW to Expand.
...
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
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use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
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Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
...
still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
94f04c6fc9
Reflects the chanegs made to PredicateOperand.
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llvm-svn: 37898
2007-07-05 07:18:20 +00:00
335c65e9a4
Silence a warning.
...
llvm-svn: 37737
2007-06-26 18:31:22 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
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llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
256144de4a
Set ARM ifcvt duplication limit to 3 for now.
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llvm-svn: 37385
2007-06-01 08:28:59 +00:00
ea623560f8
Silence some compilation warnings.
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llvm-svn: 37197
2007-05-18 01:19:57 +00:00
6addd65914
Set ARM if-conversion block size threshold to 10 instructions for now.
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llvm-svn: 37194
2007-05-18 00:19:34 +00:00
58698d2534
More effective breakdown of memcpy into repeated load/store. These are now
...
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
llvm-svn: 37179
2007-05-17 21:31:21 +00:00
1b8d46ab21
Fix previous patch. GOTOFF can be used only when the symbol has internal
...
linkage or hidden visibility.
llvm-svn: 37055
2007-05-14 23:20:21 +00:00
d705f5d51d
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
...
and used in the same module.
llvm-svn: 37044
2007-05-14 18:46:23 +00:00
33c9886001
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
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llvm-svn: 36718
2007-05-04 00:26:58 +00:00
83930198dd
Debug support for arm-linux.
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Patch by Raul Herbster.
llvm-svn: 36690
2007-05-03 20:28:35 +00:00
bef131de68
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
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llvm-svn: 36663
2007-05-03 02:00:18 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
...
llvm-svn: 36506
2007-04-27 13:54:47 +00:00
c9f22fd1a4
Darwin runtime library does not have these.
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llvm-svn: 36505
2007-04-27 08:15:43 +00:00
ee2d164f0f
Implement PIC for arm-linux.
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llvm-svn: 36324
2007-04-22 00:04:12 +00:00
502c3f48d9
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
...
llvm-svn: 35962
2007-04-13 06:50:55 +00:00
fe926e2960
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
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llvm-svn: 35909
2007-04-11 16:17:12 +00:00
9b6d69e0c2
restore support for negative strides
...
llvm-svn: 35859
2007-04-10 03:48:29 +00:00
d44e24c896
remove dead target hooks
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llvm-svn: 35846
2007-04-09 23:33:39 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
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llvm-svn: 35840
2007-04-09 22:27:04 +00:00
bd31f41daa
Typo.
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llvm-svn: 35639
2007-04-04 00:06:07 +00:00
f742e2fe70
Arm supports negative strides as well, add them. This lets us compile:
...
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
llvm-svn: 35609
2007-04-03 00:13:57 +00:00
8e168a4f36
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
...
to be folded into non-store instructions.
llvm-svn: 35601
2007-04-02 18:51:18 +00:00
6223e83f6d
add support for the 'w' inline asm register class.
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llvm-svn: 35598
2007-04-02 17:24:08 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
...
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
17d48a8bc2
Add i16 address mode.
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llvm-svn: 35551
2007-04-01 08:06:46 +00:00
1eb94d973a
implement the new addressing mode description hook.
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llvm-svn: 35521
2007-03-30 23:15:24 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
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llvm-svn: 35406
2007-03-28 01:53:55 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
...
llvm-svn: 35381
2007-03-27 16:19:21 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
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llvm-svn: 35245
2007-03-21 21:51:52 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
...
mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
f806e1cdbc
fix indentation
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llvm-svn: 35202
2007-03-20 02:25:53 +00:00
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
25d4052af6
Only ARMv6 has BSWAP.
...
Fix MultiSource/Applications/aha test.
llvm-svn: 35128
2007-03-16 22:54:16 +00:00
Rafael Espindola