2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
...
copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
...
llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
...
llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
...
bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
...
llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c610e62e46
print arbitrary constant pool entries
...
llvm-svn: 26545
2006-03-05 09:38:03 +00:00
d428e22c07
Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now.
...
It's causing an infinite loop compiling ldecod on x86 / Darwin.
llvm-svn: 26544
2006-03-05 07:30:16 +00:00
3bc4050217
Add some simple copysign folds
...
llvm-svn: 26543
2006-03-05 05:30:57 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
f29f5204cc
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
...
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
llvm-svn: 26535
2006-03-04 23:33:26 +00:00
c44f05d624
Added support for dwarf block data entries.
...
llvm-svn: 26509
2006-03-03 21:00:14 +00:00
88f0fe15a2
Adding basic structure support.
...
llvm-svn: 26505
2006-03-03 15:06:57 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
23e75f5b49
SDOperand::isOperand should not be a forwarding. It must check *this against N's operands.
...
llvm-svn: 26502
2006-03-03 06:42:32 +00:00
6b08ae8497
Added isOperand(N): true if this is an operand of N
...
llvm-svn: 26501
2006-03-03 06:24:54 +00:00
5e9a695026
A bit more tweaking
...
llvm-svn: 26500
2006-03-03 06:23:43 +00:00
55c1173a6c
Fix VC++ compilation errors.
...
llvm-svn: 26498
2006-03-03 03:25:07 +00:00
993e9cf26e
Move #include "llvm/CodeGen/AsmPrinter.h" to top since it's the interface.
...
llvm-svn: 26493
2006-03-03 02:04:29 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
4e3904f637
- Fixed some priority calculation bugs that were causing bug 478. Among them:
...
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
2006-03-02 21:38:29 +00:00
862001ad75
Support for enumerations.
...
llvm-svn: 26466
2006-03-01 23:52:37 +00:00
38d5e768b2
Don't print llvm constant in assmebly file. Assembler won't like comments that
...
span multiple lines.
llvm-svn: 26463
2006-03-01 22:18:09 +00:00
0db2f2c689
Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
...
in the dag combiner on 176.gcc on x86.
llvm-svn: 26459
2006-03-01 21:47:21 +00:00
4e71db13d6
Switch back to using actual dwarf tags. Simplifies code without loss to other
...
debug forms.
llvm-svn: 26455
2006-03-01 20:39:36 +00:00
232024edb8
Fix a typo evan noticed
...
llvm-svn: 26454
2006-03-01 19:55:35 +00:00
f770cf5b90
Use context and not compile unit.
...
llvm-svn: 26453
2006-03-01 18:20:30 +00:00
1246d5c054
I guess I can handle large type sizes.
...
llvm-svn: 26452
2006-03-01 18:13:05 +00:00
b9ac4cba66
Basic array support.
...
llvm-svn: 26451
2006-03-01 17:53:02 +00:00
bc1c85beea
Add support for target-specific dag combines
...
llvm-svn: 26443
2006-03-01 04:53:38 +00:00
fbcd62d3bb
Add a new AddToWorkList method, start using it
...
llvm-svn: 26441
2006-03-01 04:03:14 +00:00
324871ef1a
Pull shifts by a constant through multiplies (a form of reassociation),
...
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
llvm-svn: 26440
2006-03-01 03:44:24 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
be85e89ec4
- Added VConstant as an abstract version of ConstantVec.
...
- All abstrct vector nodes must have # of elements and element type as their
first two operands.
llvm-svn: 26432
2006-03-01 00:51:13 +00:00
716edb9754
Add const, volatile, restrict support.
...
Add array of debug descriptor support.
llvm-svn: 26428
2006-02-28 20:15:07 +00:00
f0032b350c
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
llvm-svn: 26419
2006-02-28 06:49:37 +00:00
bdbc4476d9
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26417
2006-02-28 06:35:35 +00:00
Jim Laskey