06aff571a3
[mips] Define a pseudo instruction which writes to both the lower and higher
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parts of the accumulators and gets expanded post-RA.
llvm-svn: 192667
2013-10-15 01:48:30 +00:00
ec67c90216
[mips] Use predicates to guard instructions using accumulator registers instead
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of relying on AddedComplexity.
llvm-svn: 192665
2013-10-15 01:21:37 +00:00
d98c99fd01
[mips] Rename isel nodes.
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llvm-svn: 192663
2013-10-15 01:12:50 +00:00
8a37f63714
Mips: Disassemble sign-extended 64 bit immediates properly.
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This doesn't change the meaning of the output, but makes look right. PR17539.
llvm-svn: 192483
2013-10-11 19:05:08 +00:00
16048332f1
[mips] Fix definition of mfhi and mflo instructions to read from the whole
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accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
llvm-svn: 192119
2013-10-07 18:49:46 +00:00
2b953d0b39
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
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llvm-svn: 191734
2013-10-01 09:48:56 +00:00
2788d3ec99
Even more spelling fixes for "instruction".
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llvm-svn: 191611
2013-09-28 13:42:22 +00:00
ff1fbda4cd
[mips] MUL should clobber HI0 and LO0.
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I cannot think of a test case that reliably triggers this bug.
llvm-svn: 191109
2013-09-20 21:22:28 +00:00
fc26cfcde7
Fixed bug when generating Load Upper Immediate microMIPS instruction.
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llvm-svn: 190746
2013-09-14 07:35:41 +00:00
3671a5441a
Support for microMIPS DIV instructions.
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llvm-svn: 190745
2013-09-14 07:15:21 +00:00
ab85278137
Support for misc microMIPS instructions.
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llvm-svn: 190744
2013-09-14 06:49:25 +00:00
3121353c99
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
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into a 5-bit or 6-bit field.
llvm-svn: 190226
2013-09-07 00:02:02 +00:00
79e38cde37
[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
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llvm-svn: 190224
2013-09-06 23:52:46 +00:00
50eebac68b
[mips] Delete unused classes and defs.
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llvm-svn: 190221
2013-09-06 23:42:58 +00:00
2c544d8ed5
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
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equivalent to "beq $zero, $zero, offset".
llvm-svn: 190220
2013-09-06 23:40:15 +00:00
dffc542123
[mips] Set instruction itineraries of loads, stores and conditional moves.
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llvm-svn: 190219
2013-09-06 23:28:24 +00:00
b936da159e
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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llvm-svn: 190154
2013-09-06 13:08:00 +00:00
457ba56b05
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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llvm-svn: 190152
2013-09-06 12:53:21 +00:00
e6ed5b72f1
[mips][msa] Added load/store intrinsics.
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llvm-svn: 189476
2013-08-28 12:04:29 +00:00
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
37e9b0dbb2
[mips] Clean up definitions of move word from/to coprocessor instructions.
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No functionality change.
llvm-svn: 189431
2013-08-28 00:42:50 +00:00
70835f6025
[mips][msa] Added bitconverts for vector types for big and little-endian
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llvm-svn: 189330
2013-08-27 09:40:30 +00:00
8277c1874a
This patch implements trap instructions for mips. The test cases are added.
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llvm-svn: 189213
2013-08-26 10:02:40 +00:00
6781fc1648
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
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load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
2013-08-20 21:08:22 +00:00
a43b56d9af
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
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assembler predicate HasStdEnd so that it is false when the target is micromips.
llvm-svn: 188824
2013-08-20 20:46:51 +00:00
2df9ee6ec8
This patch implements wait instruction for mips. Examples are added in test files.
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llvm-svn: 188537
2013-08-16 10:17:03 +00:00
babdcc8c2c
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
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Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 12:24:57 +00:00
8002a3f6d8
[mips] Rename HIRegs and LORegs.
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llvm-svn: 188341
2013-08-14 00:47:08 +00:00
3a2c2d42b8
[Mips][msa] Added initial MSA support.
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* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
llvm-svn: 188313
2013-08-13 20:54:07 +00:00
9770097727
[Mips] Support for unaligned load/store microMips instructions
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This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
llvm-svn: 188312
2013-08-13 20:19:16 +00:00
939877ee14
This patch implements ei and di instructions for mips. Test cases are added.
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llvm-svn: 188176
2013-08-12 13:07:23 +00:00
00fcf2e169
[mips] Rename accumulator register classes and FP register operands.
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llvm-svn: 188020
2013-08-08 21:54:26 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
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llvm-svn: 187832
2013-08-06 23:08:38 +00:00
e2a39e7532
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
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EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
llvm-svn: 187824
2013-08-06 22:35:29 +00:00
34a32c0b87
[mips] Replace usages of register classes with register operands. Also, remove
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unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
llvm-svn: 187821
2013-08-06 22:20:40 +00:00
21f334372e
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
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remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
llvm-svn: 187632
2013-08-01 23:14:16 +00:00
f8fff213d5
[mips] Define instruction itineraries IIArith and IILogic.
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No functionality change.
llvm-svn: 187468
2013-07-31 00:55:34 +00:00
5973e8371a
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
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turns "bal" into "bgezal".
llvm-svn: 187440
2013-07-30 20:24:24 +00:00
a3d9ab90dc
[mips] Implement llvm.trap intrinsic.
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Patch by Sasa Stankovic.
llvm-svn: 187244
2013-07-26 20:58:55 +00:00
44ff81d4e3
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
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the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
llvm-svn: 186855
2013-07-22 18:52:22 +00:00
29410f9c91
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
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llvm-svn: 186507
2013-07-17 14:05:19 +00:00
1baf2ea2d1
[mips] Add instruction itinerary classes for mult, seb and slt instructions.
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llvm-svn: 186222
2013-07-12 22:43:20 +00:00
bcf1ca08e0
Add support for Mips break and syscall insructions. The corresponding test cases are added.
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llvm-svn: 186151
2013-07-12 09:25:35 +00:00
524ad0e46e
Reverting commit r185999 due to buildboot failure.
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llvm-svn: 186000
2013-07-10 12:26:26 +00:00
e84de1e101
Add support for Mips break and syscall insructions. The corresponding test cases are added.
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llvm-svn: 185999
2013-07-10 10:18:10 +00:00
b34ad7860f
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
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floating point loads and stores.
No changes in functionality.
llvm-svn: 185399
2013-07-02 00:00:02 +00:00
1af66c9b8a
[mips] Reverse the order of source operands of shift and rotate instructions that
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have three register operands.
No intended functionality changes.
llvm-svn: 185376
2013-07-01 20:39:53 +00:00
da4496c860
[mips] brcond + setgt/setugt instruction selection patterns.
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llvm-svn: 183334
2013-06-05 19:49:55 +00:00
6871031be9
[mips] Add instruction selection patterns for blez and bgez.
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llvm-svn: 182396
2013-05-21 17:13:47 +00:00
5de4416962
[mips] Add (setne $lhs, 0) instruction selection pattern.
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llvm-svn: 182307
2013-05-20 18:18:07 +00:00
Akira Hatanaka