7 Commits

Author	SHA1	Message	Date
Bill Wendling	ead89ef63e	Don't cache the instruction and register info from the TargetMachine, because ... the internals of TargetMachine could change. llvm-svn: 183493	2013-06-07 07:04:14 +00:00
Akira Hatanaka	7b8b9b9abf	[mips] Define a function which returns the GPR register class. ... llvm-svn: 178359	2013-03-29 19:17:42 +00:00
Eli Bendersky	8da87163ca	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo ... to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788	2013-02-21 20:05:00 +00:00
Akira Hatanaka	5852e3b800	[mips] Stop reserving register AT and use register scavenger when a scratch ... register is needed. llvm-svn: 167341	2012-11-03 00:05:43 +00:00
Akira Hatanaka	4da9667631	Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class ... Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. llvm-svn: 162413	2012-08-22 23:58:53 +00:00
Akira Hatanaka	88d76cfd7a	Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits ... instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. llvm-svn: 161093	2012-07-31 23:52:55 +00:00
Akira Hatanaka	cb37e13fa7	Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and ... MipsSERegisterInfo. llvm-svn: 161092	2012-07-31 23:41:32 +00:00