Commit Graph

48690 Commits

Author SHA1 Message Date
Jakub Staszak 17af66a62f Add Zero Heurestics to BranchProbabilityInfo. If we compare value to zero we
decide whether condition is likely to be true this way:

x == 0  ->  false
x <  0  ->  false
x <= 0  ->  false
x != 0  ->  true
x >  0  ->  true
x >= 0  ->  true

llvm-svn: 136583
2011-07-31 03:27:24 +00:00
Jakob Stoklund Olesen eb5ea833ed Revert r136528 "Enable compact region splitting by default."
While this generally helped x86-64, there was some large regressions
for i386.

llvm-svn: 136571
2011-07-30 17:19:14 +00:00
Chandler Carruth 27246dc784 Switch another of the old dependencies on implicitly produced synthetic
rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.

llvm-svn: 136567
2011-07-30 10:10:23 +00:00
Bill Wendling ad088e6724 Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.

llvm-svn: 136556
2011-07-30 05:42:50 +00:00
Sean Callanan 147c83ed4d Added several architecture names.
llvm-svn: 136552
2011-07-30 01:29:54 +00:00
Jakob Stoklund Olesen 5670f850c6 Revert "Don't check liveness of unallocatable registers."
The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548
2011-07-30 00:57:25 +00:00
Jakob Stoklund Olesen 95cc5440e9 Don't check liveness of unallocatable registers.
This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

llvm-svn: 136541
2011-07-29 23:36:21 +00:00
Jakob Stoklund Olesen 9dd184151b Check for multiple defs in the machine code verifier.
llvm-svn: 136535
2011-07-29 23:02:48 +00:00
Jakob Stoklund Olesen 9760f04ef9 Add an isSSA() flag to MachineRegisterInfo.
This flag is true from isel to register allocation when the machine
function is required to be in SSA form.  The TwoAddressInstructionPass
and PHIElimination passes clear the flag.

The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.

llvm-svn: 136532
2011-07-29 22:51:22 +00:00
Jakub Staszak 0480a8fbbb Do not lose branch weights when lowering SwitchInst.
llvm-svn: 136529
2011-07-29 22:25:21 +00:00
Jakob Stoklund Olesen b5c2d3210c Enable compact region splitting by default.
This helps generate better code in functions with high register
pressure.

llvm-svn: 136528
2011-07-29 22:10:27 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Chris Lattner 34a7db7ae8 have the verifier catch gep's into opaque struct types. PR10473
llvm-svn: 136510
2011-07-29 20:32:28 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Chandler Carruth 3566477679 On mac, it seems the MC disassembler is actually using the targetinfo
for targets that don't have an MC-ized disassembler. I'm suspicious that
this shouldn't actually be happening, but hoping to fix the CMake build
on macs first, and investigate why second.

llvm-svn: 136508
2011-07-29 20:23:34 +00:00
Jakub Staszak 539db98987 Remove unneeded const_cast.
llvm-svn: 136506
2011-07-29 20:05:36 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00
Devang Patel ce0ceebb1c Clear DbgValues in the end.
llvm-svn: 136503
2011-07-29 19:49:58 +00:00
Jakub Staszak efd94c8fea Add more constantness in BranchProbabilityInfo.
llvm-svn: 136502
2011-07-29 19:30:00 +00:00
Devang Patel 3e02522fee Clean up debug info after reassociation.
llvm-svn: 136480
2011-07-29 19:00:35 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Nick Lewycky 9ee5f77141 Don't look at $PWD in GetCurrentDirectory.
llvm-svn: 136477
2011-07-29 18:26:59 +00:00
Jim Grosbach 20d38124a2 ARM SRS and RFE instructions are not code-gen only.
llvm-svn: 136475
2011-07-29 17:51:39 +00:00
Jim Grosbach 3b764cfd48 ARM range checking for mode on CPS instruction.
llvm-svn: 136473
2011-07-29 17:42:17 +00:00
Jim Grosbach e658f4faeb Update FIXME.
llvm-svn: 136470
2011-07-29 17:36:04 +00:00
Jim Grosbach 47859c8ab0 Tweak comment.
llvm-svn: 136468
2011-07-29 17:33:29 +00:00
Nick Lewycky 38b9b568b9 Teach Path::GetCurrentDirectory to use $PWD, to support users who like to do
screwy things by setting PWD != getcwd(). For example, some developers I know
will use this to control the value in gcc's DW_AT_comp_dir value in debug
output. With this patch, that trick will now work on clang too.

The only other effect of this change is that the static analysis will now
respect $PWD when reporting the directory of the files in its HTML output. I
think that's fine.

llvm-svn: 136459
2011-07-29 04:42:39 +00:00
Nick Lewycky 019d255d3e Fix a lot of typos, improve (but not necessarily fix) grammaros and reflow some
lines. No functionality change.

llvm-svn: 136458
2011-07-29 03:49:23 +00:00
Eli Friedman adec587d5c Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)

llvm-svn: 136457
2011-07-29 03:05:32 +00:00
Jakub Staszak 0978426843 Remove incEdgeWeight and decEdgeWeight. Set edge weight directly to avoid
rounding errors.

llvm-svn: 136456
2011-07-29 02:36:53 +00:00
Chandler Carruth bc836c2c84 Fix the MCDisassembler dependencies. These were just absurdly wrong.
First off, only depend on the actual MC-ized disassemblers in the
targets, not all of the libraries those in turn depend on.

Second off, only depend on those MC-ized disassemblers for targets we're
building.

This should fix builds of fewer than all targets.

llvm-svn: 136455
2011-07-29 02:12:59 +00:00
Bruno Cardoso Lopes 65ce5ea3ba Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.

llvm-svn: 136454
2011-07-29 02:05:28 +00:00
Bruno Cardoso Lopes 81eb193f2e Match VPERMIL masks more strictly and update the target specific mask
generation to always catch the weird cases.

llvm-svn: 136453
2011-07-29 01:31:15 +00:00
Bruno Cardoso Lopes 795f558532 Add DecodeShuffle shuffle support for VPERMIPD variantes
llvm-svn: 136452
2011-07-29 01:31:11 +00:00
Bruno Cardoso Lopes d23709b18c Add v8i32 and v4i64 vpermil patterns
llvm-svn: 136451
2011-07-29 01:31:07 +00:00
Bruno Cardoso Lopes c00f6728bc Fix a bug while generating target specific VPERMIL masks: skip
undef mask elements. This fixes PR10529.

llvm-svn: 136450
2011-07-29 01:31:04 +00:00
Bruno Cardoso Lopes b9ba465de8 Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.
Also tidy up code a bit.

llvm-svn: 136449
2011-07-29 01:31:02 +00:00
Bruno Cardoso Lopes 6aee388423 Cleanup PALIGNR handling and remove the old palign pattern fragment.
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

llvm-svn: 136448
2011-07-29 01:30:59 +00:00
Bill Wendling 7eadbeaf62 Use the pointer type size.
With this, we can now compile a simple EH program.

llvm-svn: 136446
2011-07-29 01:15:29 +00:00
Bill Wendling 6a8cac735a And now something that compiles...
llvm-svn: 136445
2011-07-29 01:11:33 +00:00
Bill Wendling 4b0a365beb Make sure to sext or trunc the result from the register.
llvm-svn: 136444
2011-07-29 01:11:14 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
2011-07-29 00:27:32 +00:00
Eli Friedman 530341d748 Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>
llvm-svn: 136435
2011-07-29 00:18:19 +00:00
Chandler Carruth 9d7feab3e0 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Bill Wendling 3cc87682e1 Visit the landingpad instruction.
This generates the correct SDNodes for the landingpad instruction. It makes an
assumption that the result of the landingpad instruction has at least two
values. And that the first value is a pointer to the exception object and the
second value is the "selector."

llvm-svn: 136430
2011-07-28 23:44:58 +00:00
Bill Wendling 7fa7fe6b58 Add the AddLandingPadInfo function.
AddLandingPadInfo takes a landingpad instruction and grabs all of the
information from it that it needs for EH table generation.

llvm-svn: 136429
2011-07-28 23:42:57 +00:00
Jakub Staszak eec01ccbf9 Change LBH_TAKEN_WEIGHT to 124 (from 128). Right now, sum of
LBH_TAKEN_WEIGHT + LBH_NONTAKEN_WEIGHT = 128 which in _most_ cases reduce
number of rounding errors.

llvm-svn: 136428
2011-07-28 23:42:08 +00:00
Jim Grosbach dd475c39d7 PLD and PLI are not predicable in ARM mode.
llvm-svn: 136427
2011-07-28 23:22:41 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00