Commit Graph

213 Commits

Author SHA1 Message Date
James Molloy 4c493e8050 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
Nick Lewycky 73df7e3830 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
2011-09-05 21:51:43 +00:00
Nick Lewycky f1a5f57d2f Fix typo in comment.
llvm-svn: 139122
2011-09-05 18:35:03 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols.
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
2011-09-01 23:04:27 +00:00
Owen Anderson a455a0b1e7 Fix encoding for tBcc with immediate offset operand.
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
Owen Anderson 5c160fd243 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
Owen Anderson fdf3cd7f2b Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
Owen Anderson d16fb43b1f Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
Owen Anderson 543c89fb15 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
Owen Anderson 1732c2ebf6 Clean up whitespace.
llvm-svn: 138833
2011-08-30 21:58:18 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes.
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Owen Anderson 6c70e58041 Correct encoding of BL with immediate offset.
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
Owen Anderson a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
Jim Grosbach 21a60b6f90 ARM asm backend initialize isThumbMode based on target triple.
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files
from MC.

llvm-svn: 138367
2011-08-23 20:15:21 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal).
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
Jim Grosbach f00b9ccd22 ARM Thumb blx instruction fixup has same data range as bl.
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
2011-08-18 16:57:50 +00:00
Jim Grosbach 46dd413991 ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
2011-08-17 21:51:27 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
2011-08-16 20:45:50 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
2011-08-16 17:06:20 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Benjamin Kramer de2c381331 The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Benjamin Kramer c22d50e5c3 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
2011-08-08 18:56:44 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Chandler Carruth 9d7feab3e0 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Owen Anderson 7c965e7520 Update comments.
llvm-svn: 136367
2011-07-28 17:56:55 +00:00
Oscar Fuentes a8666a3cdb Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

llvm-svn: 136328
2011-07-28 02:33:52 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Evan Cheng 481ebb0133 Support .code32 and .code64 in X86 assembler.
llvm-svn: 136197
2011-07-27 00:38:12 +00:00
Jim Grosbach d2659138da ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Evan Cheng 3a79225b4c Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
llvm-svn: 136031
2011-07-26 00:42:34 +00:00
Chandler Carruth 97c069c1d2 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Evan Cheng 5928e69d20 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
llvm-svn: 136010
2011-07-25 23:24:55 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Evan Cheng f5bf19530b Code clean up.
llvm-svn: 135954
2011-07-25 20:18:48 +00:00
NAKAMURA Takumi 287bc6bdf6 ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
llvm-svn: 135837
2011-07-23 01:16:22 +00:00
Evan Cheng f2596bc62a Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
llvm-svn: 135833
2011-07-23 00:45:41 +00:00
Evan Cheng ad5f485957 Sink ARM mc routines into MCTargetDesc.
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
2011-07-22 21:58:54 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Evan Cheng 76792992d6 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
2011-07-20 05:58:47 +00:00
Evan Cheng 2129f59637 Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
2011-07-19 06:37:02 +00:00
Evan Cheng d60fa58ba1 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
2011-07-18 20:57:22 +00:00
Evan Cheng a83b37a9db Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.

llvm-svn: 135237
2011-07-15 02:09:41 +00:00
Chandler Carruth 9a0001aedb Major update to CMake build to reflect changes in r135219 in the
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.

Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.

llvm-svn: 135234
2011-07-15 00:40:52 +00:00
Evan Cheng 1705ab00ab Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
llvm-svn: 135219
2011-07-14 23:50:31 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Evan Cheng 91111d2706 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Evan Cheng 1834f5dcb6 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
llvm-svn: 134626
2011-07-07 19:05:12 +00:00
Evan Cheng f2c2616e72 Sink feature IsThumb into MC layer.
llvm-svn: 134608
2011-07-07 08:26:46 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng 8b2bda09a5 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Evan Cheng 2bd65363a8 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
llvm-svn: 134569
2011-07-07 00:08:19 +00:00
Evan Cheng 928ce72bcd Add ARM MC registry routines.
llvm-svn: 134547
2011-07-06 22:02:34 +00:00