Commit Graph

218685 Commits

Author SHA1 Message Date
David Majnemer 11234ed7d3 [CodeGen] Use generic printAsOperand machinery instead of hand rolling it
We already know how to properly print out basic blocks in
printAsOperand, we should not roll it ourselves in
AsmPrinter::EmitBasicBlockStart.  No functionality change is intended.

llvm-svn: 256413
2015-12-25 09:37:26 +00:00
Daniel Jasper 498f558fcf clang-format: [TableGen] Support ;-less include lines.
llvm-svn: 256412
2015-12-25 08:53:31 +00:00
Rui Ueyama 2df0fd86c2 Split Writer::createSections().
This function was longer than 250 lines, which is way too long
in my own standard. This patch reduces the size. It is still
too long, but this patch should be toward the right direction.

llvm-svn: 256411
2015-12-25 07:38:58 +00:00
Rui Ueyama 89f4ec74c1 Move a function to a file where it is used.
llvm-svn: 256410
2015-12-25 07:01:09 +00:00
Rui Ueyama 7d332f5eb7 Add comments.
llvm-svn: 256409
2015-12-25 06:55:39 +00:00
Rui Ueyama a246e094bc Factor out static members from DefinedRegular.
This patch moves statically-allocated Elf_Sym objects out
of DefinedRegular class, so that the class definition becomes
smaller.

llvm-svn: 256408
2015-12-25 06:12:18 +00:00
Craig Topper b347df8757 Include IR/DerivedTypes.h instead of IR/Type.h so to match llvm change r256406.
llvm-svn: 256407
2015-12-25 05:18:31 +00:00
Craig Topper 370c8d6c6b [IR] Mark the Type subclass helper methods 'inline' and move their definitions to DerivedTypes.h so they can be inlined by the compiler.
llvm-svn: 256406
2015-12-25 04:06:20 +00:00
Craig Topper 582d8ecf6a [Transforms] Use asserts instead of ifs around llvm_unreachable. NFC
llvm-svn: 256405
2015-12-25 02:04:17 +00:00
Rafael Espindola 7f040bf658 Simplify. NFC.
llvm-svn: 256404
2015-12-25 01:00:41 +00:00
Craig Topper e6337e1ebf Revert r256399 "[Sema] ArrayRef-ize ActOnBaseSpecifiers. NFC"
It broke lldb build.

llvm-svn: 256403
2015-12-25 00:36:02 +00:00
Dan Gohman 8887d1faed [WebAssembly] Fix handling of COPY instructions in WebAssemblyRegStackify.
Move RegStackify after coalescing and teach it to use LiveIntervals instead
of depending on SSA form. This avoids a problem where a register in a COPY
instruction is stackified and then subsequently coalesced with a register
that is not stackified.

This also puts it after the scheduler, which allows us to simplify the
EXPR_STACK constraint, as we no longer have instructions being reordered
after stackification and before coloring.

llvm-svn: 256402
2015-12-25 00:31:02 +00:00
Craig Topper 99d235329f [Sema] ArrayRef-ize SubstExprs. NFC
llvm-svn: 256401
2015-12-24 23:58:29 +00:00
Craig Topper 96225a5298 [Sema] ArrayRef-ize ActOnTemplateParameterList. NFC
llvm-svn: 256400
2015-12-24 23:58:25 +00:00
Craig Topper 6550a4b17e [Sema] ArrayRef-ize ActOnBaseSpecifiers. NFC
llvm-svn: 256399
2015-12-24 23:58:20 +00:00
Craig Topper d4336e01d7 [Sema] ArrayRef-ize BuildObjCDictionaryLiteral. NFC
llvm-svn: 256398
2015-12-24 23:58:15 +00:00
Craig Topper 883dd33294 [Sema] ArrayRef-ize ParseObjCStringLiteral and CodeCompleteObjCProtocolReferences. NFC
llvm-svn: 256397
2015-12-24 23:58:11 +00:00
Ekaterina Romanova 8b27746bde Some minor correction based on David Blaikie post-commit code review for r255281.
llvm-svn: 256396
2015-12-24 22:52:41 +00:00
Sanjay Patel b28ca3f118 fix test that depends on LLVM optimizations
llvm-svn: 256395
2015-12-24 21:53:40 +00:00
Sanjay Patel ae945e7927 [InstCombine] transform more extract/insert pairs into shuffles (PR2109)
This is an extension of the shuffle combining from r203229:
http://reviews.llvm.org/rL203229

The idea is to widen a short input vector with undef elements so the
existing shuffle transform for extract/insert can kick in.

The motivation is to finally solve PR2109:
https://llvm.org/bugs/show_bug.cgi?id=2109

For that example, the IR becomes:

%1 = bitcast <2 x i32>* %P to <2 x float>*
%ld1 = load <2 x float>, <2 x float>* %1, align 8
%2 = shufflevector <2 x float> %ld1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%i2 = shufflevector <4 x float> %A, <4 x float> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x float> %i2

And x86 SSE output improves from:

movq	(%rdi), %xmm1           ## xmm1 = mem[0],zero
movdqa	%xmm1, %xmm2
shufps	$229, %xmm2, %xmm2      ## xmm2 = xmm2[1,1,2,3]
shufps	$48, %xmm0, %xmm1       ## xmm1 = xmm1[0,0],xmm0[3,0]
shufps	$132, %xmm1, %xmm0      ## xmm0 = xmm0[0,1],xmm1[0,2]
shufps	$32, %xmm0, %xmm2       ## xmm2 = xmm2[0,0],xmm0[2,0]
shufps	$36, %xmm2, %xmm0       ## xmm0 = xmm0[0,1],xmm2[2,0]
retq

To the almost optimal:

movhpd	(%rdi), %xmm0

Note: There's a tension in the existing transform related to generating
arbitrary shufflevector masks. We avoid that in other places in InstCombine
because we're scared that codegen can't handle strange masks, but it looks
like we're ok with producing those here. I purposely chose weird insert/extract
indexes for the regression tests to see the effect in these cases. 
For PowerPC+Altivec, AArch64, and X86+SSE/AVX, I think the codegen is equal or
better for these examples.

Differential Revision: http://reviews.llvm.org/D15096

llvm-svn: 256394
2015-12-24 21:17:56 +00:00
Sanjay Patel 376c06c2b9 use auto for obvious type; NFC
llvm-svn: 256393
2015-12-24 21:11:29 +00:00
Rafael Espindola 91bd48a33a Update the recorded CIE length when aligning.
We cannot just pad with 0s as that would be a terminator mark.

llvm-svn: 256392
2015-12-24 20:44:06 +00:00
Bill Seurer 8a39ce8d32 [power] Fix test case target checks
Several test cases that used to fail on both power LE and BE
now run correctly on LE.

llvm-svn: 256391
2015-12-24 20:21:36 +00:00
Dave Bartolomeo 292b31901f Fix signed/unsigned warning in Line.h.
llvm-svn: 256390
2015-12-24 19:17:54 +00:00
Dave Bartolomeo a779f5a401 Remove unused constants from TypeTableBuilder.cpp.
llvm-svn: 256389
2015-12-24 19:15:56 +00:00
Bill Seurer 8771bbfbe2 Fix case of path name
llvm-svn: 256388
2015-12-24 18:54:35 +00:00
Dave Bartolomeo dd38b1bf12 Fix CodeView library name and non-CMake builds
llvm-svn: 256387
2015-12-24 18:51:35 +00:00
Dave Bartolomeo de0bfee769 Fix initializer order warning in TypeRecord.h
llvm-svn: 256386
2015-12-24 18:25:54 +00:00
Dave Bartolomeo 89ba802b92 LLVM CodeView library
Summary: This diff is the initial implementation of the LLVM CodeView library. There is much more work to be done, namely a CodeView dumper and tests. This patch should help others make progress on the LLVM->CodeView debug info emission while I continue with the implementation of the dumper and tests.

This library implements support for emitting debug info in the CodeView format. This phase of the implementation only includes support for CodeView type records. Clients that need to emit type records will use a class derived from TypeTableBuilder. TypeTableBuilder provides member functions for writing each kind of type record; each of these functions eventually calls the writeRecord virtual function to emit the actual bits of the record. Derived classes override writeRecord to implement the folding of duplicate records and the actual emission to the appropriate destination. LLVMCodeView provides MemoryTypeTableBuilder, which creates the table in memory. In the future, other classes derived from TypeTableBuilder will write to other destinations, such as the type stream in a PDB.

The rest of the types in LLVMCodeView define the actual CodeView type records and all of the supporting enums and other types used in the type records. The TypeIndex class is of particular interest, because it is used by clients as a handle to a type in the type table.

The library provides a relatively low-level interface based on the actual on-disk format of CodeView. For example, type records refer to other type records by TypeIndex, rather than by an actual pointer to the referent record. This allows clients to emit type records one at a time, rather than having to keep the entire transitive closure of type records in memory until everything has been emitted. At some point, having a higher-level interface layered on top of this one may be useful for debuggers and other tools that want a more holistic view of the debug info. The lower-level interface should be sufficient for compilers and linkers to do the debug info manipulation that they need to do efficiently.

Reviewers: rnk, majnemer

Subscribers: silvas, rnk, jevinskie, llvm-commits

Differential Revision: http://reviews.llvm.org/D14961

llvm-svn: 256385
2015-12-24 18:12:38 +00:00
Rafael Espindola 1119191c4f Make it possible to create common symbols from bitcode.
Since the only missing bit was the size, I just replaced the Elf_Sym
with the size.

llvm-svn: 256384
2015-12-24 16:23:37 +00:00
Rafael Espindola 02ce26a1b4 Delete DefinedAbsolute.
There are 3 symbol types that a .bc can provide during lto: defined,
undefined, common.

Defined and undefined symbols have already been refactored. I was
working on common and noticed that absolute symbols would become an
oddity: They would be the only symbol type present in a .o but not in
a.bc.

Looking a bit more, other than the special section number they were only
used for special rules for computing values. In that way they are
similar to TLS, and we don't have a DefinedTLS.

This patch deletes it. With it we have a reasonable rule of the thumb
for having a symbol kind: It exists if it has special resolution
semantics.

llvm-svn: 256383
2015-12-24 14:22:24 +00:00
Marina Yatsina 59d35f1415 [X86][ms-inline asm] Test case for adding support for memory operands that include structs
Test case for commit 256381

Differential Revision: http://reviews.llvm.org/D15749

llvm-svn: 256382
2015-12-24 12:11:40 +00:00
Marina Yatsina 8dfd5cbb73 [X86][ms-inline asm] Add support for memory operands that include structs
Add ability to reference struct symbols in memory operands.
Test case will be added on the clang side (review http://reviews.llvm.org/D15749)

Differential Revision: http://reviews.llvm.org/D15748

llvm-svn: 256381
2015-12-24 12:09:51 +00:00
Rui Ueyama 01a65b19cf Add comments.
llvm-svn: 256380
2015-12-24 10:37:32 +00:00
Rui Ueyama 74f598b2b5 Remove `continue` to make the code a bit shorter. NFC.
llvm-svn: 256379
2015-12-24 10:14:05 +00:00
Rui Ueyama da735325fa Mark .eh_frame sections as live by default. NFC.
This change eliminates a string comparison from the
garbage collector.

llvm-svn: 256378
2015-12-24 10:08:54 +00:00
Benjamin Kramer b42d9a5f06 Replace llvm::utostr calls in Twine context with Twines. NFC.
llvm-svn: 256377
2015-12-24 10:07:37 +00:00
Davide Italiano b40553751a [README] Update to reflect the new world order.
llvm-svn: 256376
2015-12-24 10:03:46 +00:00
Benjamin Kramer 7a5c8c8fe3 [ProfileData] Make helper function static.
No functional change.

llvm-svn: 256375
2015-12-24 10:03:37 +00:00
Benjamin Kramer fe2b541546 [FunctionImport] Move pass into anonymous namespace.
No functional change.

llvm-svn: 256374
2015-12-24 10:03:35 +00:00
Davide Italiano bcbfedc927 [ELF] Don't reclaim .ctors/.dtors sections.
In FreeBSD, rtld expects .ctors containing -1 (0xffffffff), and a
.ctors section containing the correct bits is provided to the linker as
input (/usr/lib/crtbegin.o).

Contents of section .ctors:
 0000 ffffffff ffffffff                    ........

This section is not stripped even if not referenced or empty, also in
gold or ld.bfd. It would be nice to strip it when not needed but
since existing object files rely on that we can't do better to keep it
around.

Differential Revision:   http://reviews.llvm.org/D15767

llvm-svn: 256373
2015-12-24 09:52:11 +00:00
Rui Ueyama 7924fb8142 Add a comment.
llvm-svn: 256372
2015-12-24 09:50:22 +00:00
Chandler Carruth 85dbea99ee Add a missing const qualifier on the context instruction. This somehow
has always been missing. =/

llvm-svn: 256371
2015-12-24 09:08:08 +00:00
Rui Ueyama 3d312a684a Remove unnecessary explicit instantiation.
llvm-svn: 256370
2015-12-24 08:41:55 +00:00
Rui Ueyama 3f11c8c97e Split functions and add comments. NFC.
llvm-svn: 256369
2015-12-24 08:41:12 +00:00
Rui Ueyama 3bfaba928f Make a member function non-member. NFC.
llvm-svn: 256368
2015-12-24 08:37:34 +00:00
Rui Ueyama dc8d3a2104 Return early and remove a redundant error check. NFC.
llvm-svn: 256367
2015-12-24 08:36:56 +00:00
Asaf Badouh 9a5a83a518 [X86][PKU] Add {RD,WR}PKRU encoding
Differential Revision: http://reviews.llvm.org/D15711

llvm-svn: 256366
2015-12-24 08:25:00 +00:00
Elena Demikhovsky 9e225a2f52 AVX-512: Kreg set 0/1 optimization
The patterns that set a mask register to 0/1
KXOR %kn, %kn, %kn / KXNOR %kn, %kn, %kn
are replaced with
KXOR %k0, %k0, %kn / KXNOR %k0, %k0, %kn - AVX-512 targets optimization.

KNL does not recognize dependency-breaking idioms for mask registers,
so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
Using %k0 as the undef input register is a performance heuristic based
on the assumption that %k0 is used less frequently than the other mask
registers, since it is not usable as a write mask.

Differential Revision: http://reviews.llvm.org/D15739

llvm-svn: 256365
2015-12-24 08:12:22 +00:00
Igor Breger 268f6f53c5 AVX512: VPMOVM2B/W/D/Q intrinsic implementation.
Differential Revision: http://reviews.llvm.org//D15747

llvm-svn: 256364
2015-12-24 07:11:53 +00:00